Reduced Parameter Fluctuation with Laser and Flash Lamp Anneal for 65nm Volume Production

Abstract

Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.

Advanced Annealing Schemes for High-Performance SOI Logic Technologies

“…Nevertheless, process parameter fluctuations have a strong impact on functionality and performance of logic circuits and memory cells and they should be as small as possible. The analysis of volume production data has shown that the control of the sRTA temperature is equally important to the control of the lengths and widths of the transistors gates [5].…”