22FDX TM is the industry's first FDSOI technology double-patterning steps required at the 16/14nm FinFET architected to meet the requirements of emerging mobile, technology nodes. Approximately 75% of the process steps Internet-of-Things (IoT), and RF applications. This platform are common with the 28nm platform enabling high yield achieves the power and performance efficiency of a 16/14nm capability. The gate-first High-K Metal Gate (HKMG) FinFET technology in a cost effective, planar device integration is used to ensure a low cost process flow [3]. A architecture that can be implemented with ~30% fewer typical cross-section of nFET and pFET devices is shown in masks. Performance comes from a second generation FDSOI Fig.1. All active devices are built on SOI whereas passive transistor, which produces nFET (pFET) drive currents of devices and select active devices, such as LDMOS, are 910μA/μm (856μA/μm) at 0.8V and 100nA/μm Ioff. For conventionally formed in the bulk substrate (Fig.2). In ultra-low power applications, it offers low-voltage operation addition to the introduction of FDSOI substrates, new process down to 0.4V Vmin for 8T logic libraries, as well as 0.62V and modules are introduced to support back-bias capability, 0.52V V min for high-density and high-current bitcells, ultra-passive device fabrication, enhanced device performance and low leakage devices approaching 1pA/µm Ioff, and body-technology scale factor (Fig.3). The introduction of a SiGe biasing to actively trade-off power and performance. channel for pFET devices by the condensation technique [4] Superior RF/Analog characteristics to FinFET are achieved and SOI thickness <7nm enable high DC drive currents. A including high f T /f MAX of 375GHz/290GHz and post STI hybrid etch process is used to form back gate 260GHz/250GHz for nFET and pFET, respectively. The contacts and enable the implementation of devices and taphigh f MAX extends the capabilities to 5G and millimeter wave cells in the bulk substrate (Fig.4). Dual in-situ doped epi (>24GHz) RF applications. processes (Si:P and SiGe:B) are formed in combination with a low-k spacer to ensure highly doped source/drain regions I. INTRODUCTION while maintaining low gate-to-drain capacitance (critical for Rising manufacturing costs and emerging applications RF applications). Technology CPP is scaled without adding requiring unparalleled energy efficiency are driving the need extra masking steps relative to the 28nm Front-End-of-Line. for new semiconductor device solutions. For the first time, Dual patterning techniques are used to scale M1/M2 pitch, an increase in the cost per die is observed with the leading to a logic/SRAM die scaling of 0.72x/0.83x relative to introduction of 16/14nm FinFET technologies due to the 28nm Poly/SiON technology node. increased process complexity and mask count. Cost sensitive B. Device Performance IoT and mobile applications are driving new requirements such as increased integration, advanced power management, Device construction utilizes either flip well (SLVT/LV...

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In a system consisting of two different lattices, the structural stability is ensured when an epitaxial relationship occurs between them and allows the system to retain the stress, avoiding the formation of a polycristalline film. The phenomenon occurs if the film thickness does not exceed a critical value. Here we show that, in spite of its orthorombic structure, a 14nm-thick NiSi layer can threedimensionally (3D) adapt to the cubic Si lattice by forming transrotational domains. Each domain arises by the continuous bending of the NiSi lattice, maintaining a close relationship with the substrate structure. The presence of transrotational domains does not cause a roughening of the layer but instead it improves the structural and electrical stability of the silicide in comparison with a 24nm-thick layer formed using the same annealing process. These results have relevant implications on thickness scaling of NiSi layers currently used as metallizations of electronic devices.Correspondence should be addressed to : Alessandra Alberti ( Alessandra.Alberti@imm.cnr.it) Acta Crystallographica B, 61, 486-491 (2005) 2

A critical review is given on phenomenological models of damage accumulation used in binary collision (BC) computer simulations of the dose dependence of the shape of as-implanted profiles and of the interdependence of channeling and damage buildup. The statistical approach, which assumes the accumulation of amorphous pockets, is found to be the most realistic model for doses below the amorphization threshold. The dynamic simulation of the formation of amorphous layers is described by an improved model. If within a certain depth interval the density of amorphous pockets exceeds a critical value, abrupt amorphization occurs. The model is applied in the Crystal-TRIM code. Using only two empirical parameters, the change of the shape of range distributions with growing dose as well as the formation of amorphous layers during ion bombardment can be simulated. One parameter describes the accumulation of amorphous pockets and depends on the target temperature. The other parameter is independent of temperature and models the onset of amorphization. Results of Crystal-TRIM calculations for B, BF, P, and As implantations are compared with a comprehensive set of experimental data on range and damage profiles obtained by secondary ion mass spectroscopy, cross-sectional transmision electron microscopy, and channeling Rutherford backscattering spectroscopy. In general, good agreement between simulations and measurements is found.