According to the 2001 International TechnologyRoadmap for Semiconductors (ITRS) one of the key challenges for source/drain extension technology at the 100 nm technology node and beyond is to produce a junction in the range of a few tens of nanometers with low sheet resistance values. To achieve the requirements of the ITRS, a deep understanding of the diffusion, activation and the dopant-defect interaction is necessary. In this paper the temperature-time profile of spike anneals is varied. The temperature of the pre-stabilization step was set between 600°C and 800°C for 10 s. The pre-stabilization step was followed by a constant spike-annealing condition to achieve high electrical activation, and for reference each prestabilization condition was also used to process wafers without additional spike-annealing. The effects of these variations in the thermal budget in the low temperature regime were evaluated for the implant species 11 B + and 49 BF 2 + and for diverse implant energies and doses. All the data are analyzed and discussed with respect to the junction depth versus sheet resistance figure. With the pre-stabilization at 650°C for 10 s followed by the spike anneal the best results with respect to junction depth and sheet resistance are achieved.
Process parameter fluctuations have a strong impact on functionality and performance of CMOS logic circuits and memory cells. Tight control of transistor gate length and final anneal temperature are equally important. We have developed a strategy to monitor these fluctuations which takes into account the full complexity of advanced microprocessors with large cache cell areas. This paper shows that reducing the anneal temperature reduces the parameter fluctuations. Transistor performance degradation at reduced temperatures can be compensated by using advanced annealing techniques like Laser or Flash lamp anneal. These techniques do not result in additional parameter fluctuation.
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