Dependence of junction depth and sheet resistance on the thermal budget in the low temperature pre-stabilization regime

Abstract

According to the 2001 International TechnologyRoadmap for Semiconductors (ITRS) one of the key challenges for source/drain extension technology at the 100 nm technology node and beyond is to produce a junction in the range of a few tens of nanometers with low sheet resistance values. To achieve the requirements of the ITRS, a deep understanding of the diffusion, activation and the dopant-defect interaction is necessary. In this paper the temperature-time profile of spike anneals is varied. The temperature of the pre-stabilization step was set between 600°C and 800°C for 10 s. The pre-stabilization step was followed by a constant spike-annealing condition to achieve high electrical activation, and for reference each prestabilization condition was also used to process wafers without additional spike-annealing. The effects of these variations in the thermal budget in the low temperature regime were evaluated for the implant species 11 B + and 49 BF 2 + and for diverse implant energies and doses. All the data are analyzed and discussed with respect to the junction depth versus sheet resistance figure. With the pre-stabilization at 650°C for 10 s followed by the spike anneal the best results with respect to junction depth and sheet resistance are achieved.

Implant Annealing – An Evolution from Soak over Spike to Millisecond Annealing

“…To ensure good process uniformity, repeatability and temperature control, a pre-stabilization step at an intermediate temperature is usually used [18]. Bayha et al [19] investigated the influence of different pre-stabilization temperatures followed by a spike anneal to 1050 °C peak temperature on sheet resistance and junction depth on 500 eV 11 B + and 1.1 and 2.2 keV 49 BF 2 + implanted junctions with doses of 1 and 5 . 10 15 cm -2 .…”

“…At a boron concentration of 3 . 10 18 cm -3 the junction depth of the reference sample is 34.2 nm whereas the 10 keV and 22 19 F + co-implanted wafers show junction depths of 28.7 nm and 28.1 nm respectively.…”

“…10 15 cm -2 ) and 11 B + implantation (500 eV, 1 . 10 15 cm -2 ) for various 19 F + implant conditions and spike anneal temperatures (the lines are to guide the eyes only) [38].…”

Understanding of Boron Junction Stability in Preamorphized Silicon after Optimized Flash Annealing

“…11,12 However, extensive defects remain after flash annealing, leading to high current leakage at device level. [12][13][14][15] Another main concern of the residual EOR defects is its impact on the junction stability, which is closely related to the dopant deactivation when the activated junction is subjected to postthermal treatment, such as spacer formation and silicidation, in the typical CMOS process flow. 15,16 Recently, first results from Poon et al have demonstrated that flash conditions can be optimized to improve junction characteristics.…”

“…[12][13][14][15] Another main concern of the residual EOR defects is its impact on the junction stability, which is closely related to the dopant deactivation when the activated junction is subjected to postthermal treatment, such as spacer formation and silicidation, in the typical CMOS process flow. 15,16 Recently, first results from Poon et al have demonstrated that flash conditions can be optimized to improve junction characteristics. 17,18 In this paper we perform an extensive study on the junction stability after processing with the optimized multiple-pulse and prespike RTA flash annealing.…”