It is demonstrated that focused-ion-beam written in-plane-gate transistors, working at room temperature can be realized on (100) silicon-on-insulator wafers, separated by implanted oxygen, without the need for epitaxial growth processes. Typical channel widths are in the sub-μm range. Their electrical features at room temperature are characterized by transport and Hall measurements. The channel current is measured as a function of the geometrical channel width and the implanted dose. Activation of the implanted gallium by rapid thermal annealing changes the character of the insulating lines from Ohmic barriers to npn-junctions. Consequently the leakage current across the barriers decreases significantly, the direct current output characteristics of the transistors are improved with higher implantation doses and smaller geometrical channel widths are achievable.
This letter demonstrates that the conventional two-element lumped model can provide valid capacitance-voltage (C-V) characteristics for gate oxides with large tunneling current, if the gate length is reduced. The two-element models generally suffer from severe distortion of C-V due to tunneling current, resulting in poor oxide thickness extraction. The distortion can be suppressed using high frequencies in series model or using short gate lengths in parallel model. Considering instrument limits and manufacturability, however, the parallel model is more desirable. The distortion can be completely suppressed up to 10 4 A/cm 2 of tunneling current, using gate lengths shorter than 0.2 m in parallel model.
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