Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Yang, H.S.; Malik, R.; Narasimha, S.; Li, Y.; Divakaruni, R.; Agnello, P.; Allen, Scott D.; Antreasyan, A.; Arnold, John; Bandy, K.; Belyansky, M.; Bonnoit, Alyssa; Bronner, G.; Chan, V.; Chen, X.; Chen, Z.; Chidambarrao, D.; Chou, A.; Clark, William F.; Crowder, S.; Engel, Brad N.; Harifuchi, H.; Huang, Shih-Fen; Jagannathan, R.; Jamin, F.; Kohyama, Y.; Kuroda, Hideaki; Lai, Chun‐Mei; Lee, H.K.; Lee, W.-H.; Lim, Eunjung; Lai, Wei-Chih; Mallikarjunan, A.; Matsumoto, Kazuya; McKnight, A.; Nayak, Jhilirani; Ng, H.; Panda, Soumya Ranjan; Rengarajan, R.; Steigerwalt, Michael; Subbanna, S.; Subramanian, K.A.; Sudijono, J.; Sudo, G.; Sun, S.-P.; Tessier, B.L.; Toyoshima, Y.; Tran, Phuong; Wise, R.; Wong, Roy K.-Y.; Yang, I.Y.; Wann, C.; Su, Lixin; Horstmann, Μ.; Feudel, T.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, Matthias; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, Μ.; Salz, H.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, Ralf van; Graßhoff, G.; Schwan, C.; Ehrichs, E. E.; Goad, S.; Buller, J.F.; Krishnan, S.; Greenlaw, D.; Raab, M.; Kepler, N.

doi:10.1109/iedm.2004.1419385

Cited by 98 publications

(38 citation statements)

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“…The final device structure features a tensile stress liner on nMOS and a compressive stress liner on pMOS on the same wafer as shown in Figure 6 from IBM's 65-nm CMOS technology [31]. DSL was demonstrated to improve nMOS and pMOS drive currents by 11% and 20%, respectively, for a sub 45-nm gate length CMOS [30].…”

Section: Dual Stress Liners (Dsl)mentioning

confidence: 98%

“…Although mechanical stress effect of etch-stop SiN liner and its impact and optimization on deep submicron CMOS transistors has been reported before [28,29], it is not until 90-nm technology node that dual stress liners (DSL) were integrated to the advanced CMOS manufacturing led by IBM [30]. In contrast to eSiGe and SMT that induce advantageous strain for either nMOS or pMOS, DSL was developed to induce both tensile strain for nMOS and compressive strain for pMOS simultaneously.…”

Section: Dual Stress Liners (Dsl)mentioning

confidence: 98%

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Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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The introduction and advancement of strain engineering has been one of the most critical features for the state-of-the-art nanoscale CMOS transistors. This paper provides an overview of the major strain engineering techniques that have remarkably re-shaped the advanced CMOS transistor architecture, including embedded SiGe (eSiGe), embedded Si:C (eSi:C), stress memorization technique (SMT), dual stress liners (DSL), and stress proximity technique (SPT). The advent of high-K/metal-gate (HKMG) also brings in additional strain benefit with its metal gate stressor (MGS) and replacement gate (RMG) process. Strain engineering continues to evolve and will remain to be one of the key performance enablers for the future generation of CMOS technologies. CitationYang B, Cai M. Advanced strain engineering for state-of-the-art nanoscale CMOS technology. Sci China Inf Sci, 2011, 54: 946-958,

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Section: Dual Stress Liners (Dsl)mentioning

confidence: 98%

Section: Dual Stress Liners (Dsl)mentioning

confidence: 98%

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Yang

Cai

2011

Sci. China Inf. Sci.

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“…Embedded SiGe (eSiGe) source/drain (S/D) structure is widely used to enhance pMOS performance, while the highly tensile silicon nitride capping layer is adopted to induce tensile strain in the nMOS channel region to enhance electron mobility [56] . This technique can also be applied to pMOS and developed as a dual-stress-liner (DSL) process (compressive stress SiN film over pMOS region and tensile stress SiN film over nMOS region) which results in the saturated drive current enhancement of 11% and 20% for nMOS and pMOS respectively [57] .…”

Section: Mobility Enhancement Technologymentioning

confidence: 99%

Challenges of 22 nm and beyond CMOS technology

Huang

Kang

et al. 2009

Sci. China Ser. F-Inf. Sci.

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It is predicted that CMOS technology will probably enter into 22 nm node around 2012. Scaling of CMOS logic technology from 32 to 22 nm node meets more critical issues and needs some significant changes of the technology, as well as integration of the advanced processes. This paper will review the key processing technologies which can be potentially integrated into 22 nm and beyond technology nodes, including double patterning technology with high NA water immersion lithography and EUV lithography, new device architectures, high K/metal gate (HK/MG) stack and integration technology, mobility enhancement technologies, source/drain engineering and advanced copper interconnect technology with ultra-low-k process.

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“…With this approach, a strained SiN cap layer, which is called CESL (contact etch stop layer), is deposited on the device's surface to generate the stress [4][5][6]. However, while CMOS integrate circuit is considered, a single CESL cannot meet the requirement for that the strained P MOS and N MOS need compressive and tensile SiN cap layers respectively [6,7].This makes related fabrication process complicated.…”

Section: Introductionmentioning

confidence: 99%

Trench based stress modulation structure for 90nm-gate CESL strained N MOSFET

Luo¹,

Tan²,

Wang³

et al. 2017

Proceedings of the 2017 2nd International Conference on Automation, Mechanical Control and Computational Engineering (AMCCE 201

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Abstract.A novel trench based stress modulation structure for strained 90nm-gate N MOSFET is demonstrated in this letter. The numerical simulation using SENTAURUS SPROCESS shows that, with this structure, the channel stress can be changed from compressive to tensile in a case of compressive CESL strained device. The relationships between the channel stress and the trenches' size are also investigated and it is deduced that the optimized trench depth and width can both be set to be 0.4um. With the trenches' size optimized, the trench based device can achieve an output current 24% higher than that of the N MOSFET without the trench based structure.

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Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Cited by 98 publications

References 0 publications

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Advanced strain engineering for state-of-the-art nanoscale CMOS technology

Challenges of 22 nm and beyond CMOS technology

Trench based stress modulation structure for 90nm-gate CESL strained N MOSFET

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