Taking SOI substrates and low-k dielectrics into high-volume microprocessor production

Greenlaw, D.; Burbach, G.; Feudel, Thomas; Feustel, F.; Frohberg, K.; Graetsch, F.; Graßhoff, G.; Hartig, Carsten; Heller, T.; Hempel, Klaus; Horstmann, Μ.; Huebler, P.; Kirsch, R.; Kruegel, S. L.; Langer, E.; Pawlowitsch, A.; Ruelke, H.; Schuehrer, H.; Stephan, R.; Wei, A.; Werner, Thomas R.; Wieczorek, K.; Raab, M.

doi:10.1109/iedm.2003.1269278

Cited by 16 publications

(8 citation statements)

References 2 publications

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“…The N-channel devices studied in this paper were selected from a 90 nm node partially depleted (PD) SOI CMOS technology [20], with physical gate oxide thickness t OX $ 1.5 nm, printed channel length L G $ 55 nm, SOI film thickness t Si = 70 nm and buried oxide t BOX = 150 nm. The devices incorporated body contacts that could be left floating (FB configuration), connected to ground (GB configuration) or biased (BB configuration) during the experiment.…”

Section: Methodsmentioning

confidence: 99%

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

Ioannou

2007

Solid-State Electronics

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Section: Methodsmentioning

confidence: 99%

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

Ioannou

2007

Solid-State Electronics

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“…The starting substrate is an integral element for sustaining overall IC performance improvement. SOI is used in volume production today for high performance microprocessors [1]. At the substrate level the critical elements are SOI and buried oxide layer uniformity, layer integrity, i.e.…”

Section: Introductionmentioning

confidence: 99%

SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures

Delprat

Boedt²,

David

et al. 2009

2009 IEEE International SOI Conference

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Fully depleted (FD) MOSFET architecture for sub-32 nm technology node requires a new SOI substrate fabrication to meet all the stringent specifications imposed by a FD device. Ultra Thin SOI (UTSOI) targets planar device architectures, stressing specifications for thickness uniformity. Also Ultra Thin Burried Oxyde (UTBOx) offers additional benefits such as the application of back bias, for example enhancing device stability or threshold voltage tuning. In this paper, we discuss the Smart Cut™ technology capability for both UTSOI and UTBOx substrate design with the quality and specifications that meet the future FD technology requirements.

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“…1 Substrate engineering such as combining sSi and silicon on insulator ͑SOI͒ technologies 2,3 made it possible to improve the IC performance by increasing the drive current and reducing leakage and power consumption. 4 Two types of substrates at wafer level are evaluated by the IC industry: sSi directly on insulator 2,4 and strained silicon on relaxed silicon germanium on insulator. 5 For both approaches high quality strain-relaxed SiGe layers grown on a Si substrate are required as virtual substrates.…”

Section: Introductionmentioning

confidence: 99%

Si + ion implantation for strain relaxation of pseudomorphic Si1−xGex/Si(100) heterostructures

Buca

Minamisawa

Trinkaus

et al. 2009

Journal of Applied Physics

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A mechanism of strain relief of pseudomorphic Si 1−x Ge x / Si͑100͒ heterostructures by Si + ion implantation and annealing is proposed and analytically modeled. The degree of strain relaxation is presented as a function of Ge content and implantation and annealing parameters. Rutherford backscattering spectrometry/channeling, Raman spectroscopy, and transmission electron microscopy are employed to quantify the efficiency of the relaxation process and to examine the quality of the samples, respectively. The mechanism and the conditions for strain relaxation are discussed in terms of dislocation loop formation in the implanted range with emphasis on loop formation in the compressively strained SiGe layer. The detrimental effect of local amorphization of the SiGe layer on its relaxation and on strain transfer to the Si-cap layer is also addressed.

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Taking SOI substrates and low-k dielectrics into high-volume microprocessor production

Cited by 16 publications

References 2 publications

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

Some issues of hot-carrier degradation and negative bias temperature instability of advanced SOI CMOS transistors

SOI substrate readiness for 22/20 nm and for fully depleted planar device architectures

Si + ion implantation for strain relaxation of pseudomorphic Si1−xGex/Si(100) heterostructures

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