No abstract

No abstract

No abstract

No abstract

No abstract

This article for the first time reports the design and performance optimization of Junctionless (JL) Bottom spacer (BSP) FinFET. Initially to get the desired value of workfunction (∅_m) and fin thickness (Tfin) for analog/RF analysis, the optimization of these parameters has been done by considering several values. It has been noticed that the increase in ∅_m and reduction in Tfin can lead to better electrical performance with suppressed short channel effects (SCE). Further, it is also observed that reduction in bottom spacer height (HBSP) can fetch enhanced analog/RF performance considering the improvement noticed in transconductance (gm), intrinsic gain (AV), transconductance generation factor (TGF), cutoff frequency (fT), and Gain frequency product (GFP). Moreover, when the bottom spacer dielectric permittivity (KBSP) is increased from 3.9 to 22, it has been found that the analog/RF performance degrades significantly.

No abstract

 Abstract-For sub-20nm FinFET and nanowire CMOS devices, NBTI is an important reliability issue, and requires an accurate model to predict device and circuit performance. In this paper, we report well calibrated predictive and scalable compact Verilog-A based compact model, integrated with NBTI model for nanowire (NW) CMOS circuit simulation and design. The stress and recovery NBTI model for Si NW FET is obtained from experimental NW pMOSFETs using range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar MOSFETs. This is attributed to its cylindrical gate structure resulting in enhanced 2-D hydrogen diffusion and stress induced Si/SiO 2 traps. This emphasizes need for evaluating NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, and interface states generation, inverter delay and RO frequency degrades rapidly and saturates in long term 10-year lifetime. Finally, design of SRAM cell employing multi-wire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using appropriate design configuration. This study underscores need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at device and circuit level. Index Terms-CompactModeling, Negative Bias Temperature Instability (NBTI), Stress and Recovery Modeling, Silicon nanowire FET/CMOS, Si NW SRAM.