Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Abstract

 Abstract-For sub-20nm FinFET and nanowire CMOS devices, NBTI is an important reliability issue, and requires an accurate model to predict device and circuit performance. In this paper, we report well calibrated predictive and scalable compact Verilog-A based compact model, integrated with NBTI model for nanowire (NW) CMOS circuit simulation and design. The stress and recovery NBTI model for Si NW FET is obtained from experimental NW pMOSFETs using range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar MOSFETs. This is attributed to its cylindrical gate structure resulting in enhanced 2-D hydrogen diffusion and stress induced Si/SiO 2 traps. This emphasizes need for evaluating NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, and interface states generation, inverter delay and RO frequency degrades rapidly and saturates in long term 10-year lifetime. Finally, design of SRAM cell employing multi-wire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using appropriate design configuration. This study underscores need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at device and circuit level. Index Terms-CompactModeling, Negative Bias Temperature Instability (NBTI), Stress and Recovery Modeling, Silicon nanowire FET/CMOS, Si NW SRAM.

A Novel Vertically Stacked Circular Nanosheet FET for High-Performance Applications

“…Furthermore, a novel device is proposed with the stacking of multiple Nanosheets in circular layout geometry. The results show that SC-NSFETs give improved electrical performance, with an ON/ OFF current ratio of more than10 5 , and a very excellent drive current of nearly 5 mA with similar foot-print. These novel SC-NSFETs are a good alternative technology for building high-current-rate integrated circuits, such as current drivers and power stages, while reducing the die size and chip cost for future scalability.…”

“…It is a difficult task to control SCEs transforming into transistors. To address SCEs, multi-gate MOSFET architectures like FinFETs, 1,2 gate-all-around (GAA) FETs, 3,4 and nanowire FETs 5,6 have been proposed.…”

Analysis of the Negative-Bias-Temperature-Instability on Omega-Gate Silicon Nanowire SOI MOSFETs with Different Dimensions

“…The NBTI can also be explained through the stress oxide electric field at the Si-SiO2 interface (Eox), which is expressed by equation (1) for NW [5] and equation 2for planar device [13]:…”

“…The omega-gate nanowire transistors present a cylindrical structure providing a higher electric field when compared to planar devices. Furthermore, this cylindrical structure presents a higher defect density in the gate oxide due to processes fabrication, and this high stress level caused by the electric field and the defects in the oxide turns the device more susceptible to NBTI effects [5] [6].…”

Sub-1-V–60 nm vertical body channel MOSFET-based six-transistor static random access memory array with wide noise margin and excellent power delay product and its optimization with the cell ratio on static random access memory cell

“…Therefore, advanced technologies for SRAMs have been extensively studied, for example, new SRAM cell structures, 1) new SRAM array architectures 2,3) and SRAMs with the applied three-dimensional (3D) structured MOSFETs such as FinFETs, 4,5) tri-gates, 6,7) and nanowire MOSFETs. 8,9) A circuit diagram for a six-transistor (6T) SRAM cell, which is generally used for SRAMs, is shown in Fig. 1.…”