In this study, with the aim to achieve a wide noise margin and an excellent power delay product (PDP), a vertical body channel (BC)-MOSFETbased six-transistor (6T) static random access memory (SRAM) array is evaluated by changing the number of pillars in each part of a SRAM cell, that is, by changing the cell ratio in the SRAM cell. This 60 nm vertical BC-MOSFET-based 6T SRAM array realizes 0.84 V operation under the best PDP and up to 31% improvement of PDP compared with the 6T SRAM array based on a 90 nm planar MOSFET whose gate length and channel width are the same as those of the 60 nm vertical BC-MOSFET. Additionally, the vertical BC-MOSFET-based 6T SRAM array achieves an 8.8% wider read static noise margin (RSNM), a 16% wider write margin (WM), and an 89% smaller leakage. Moreover, it is shown that changing the cell ratio brings larger improvements of RSNM, WM, and write time in the vertical BC-MOSFET-based 6T SRAM array.
Focused ion beam (FIB) has been applied to micro/nanometer-scale fabrication to control surface functions with the surface topographies. Although the resolution of the FIB sputtering is in the nanometer-scale range in positioning, the removal shape in the depth direction cannot be controlled numerically. This study presents a removal model to predict the surface profile in the simulation. The removal rate depends on not only the ion beam intensity but also the incident angle onto the surface to be structured. The removal model considers the effects of those two parameters to control the surface profile in sputtering. The removal rates in sputtering of the inclined surfaces at incident angles are associated with a Gaussian distribution. The parameters in the model were identified to minimize the simulation error validated against the sputtering tests. The presented model was applied to simulate the microscale structures on surfaces using the identified parameters. The simulation was validated in comparison with the actual machined shapes.
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