Low power SRAM design for 14nm GAA Si-nanowire technology

Kaushal, Gaurav; Jeong, Hong; Maheshwaram, Satish; Manhas, S. K.; Dasgupta, S.; Jung, Seong‐Ook

doi:10.1016/j.mejo.2015.10.016

Cited by 10 publications

(7 citation statements)

References 24 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…read AT (RAT), is an important metric, which depends on read cell current through the access and pull‐down transistors. Similarly, the write AT (WAT) during the write mode is measured between the time when WL reaches to 50% of VDD and node V2 reaches to switching threshold voltage of the other inverter [24, 25]. Saini and Choudhary [19] suggested that the relative change in on‐current ( I on ) and device capacitance ( C gg ) is the prime factor to investigate the delay of the circuit.…”

Section: T Sram Design and Analysismentioning

confidence: 99%

See 1 more Smart Citation

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

View full text Add to dashboard Cite

This work investigates the delay performance of junctionless silicon nanotube (JLSiNT) field-effect transistor (FET) based 6T SRAM cell. The study demonstrates that the delay performance of symmetric drain/source DS-JLSiNT FET (inner gate covers drain, channel, and source regions) based 6T SRAM gets improved when the inner gate of nanotube covers only either drain and channel regions (D-JLSiNT FET) or source and channel regions (S-JLSiNT FET) because of improved I on /C gg. The improvement in read (write) access time is ∼22% (17%) and ∼9% (20%) when DS-JLSiNT FET is replaced by D-JLSiNT FET and S-JLSiNT FET, respectively, in DS-JLSiNT FET based 6T SRAM. Furthermore, due to partial covering of inner gate, the gate electrostatic integrity is reduced which decreases the ratio of on-current to off-current (I on /I off) resulting in degraded static noise margin (SNM). However, the deterioration in write SNM, hold SNM, and read SNM are almost minimal (∼0.3, 0.9, and 2%, respectively) for S-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. However, the deterioration in SNMs is aggravated for D-JLSiNT FET based SRAM as compared to DS-JLSiNT FET based SRAM. Thus, S-JLSiNT FET is the best configuration for designing of JLSiNT FET based 6T SRAM cell.

show abstract

Section: T Sram Design and Analysismentioning

confidence: 99%

“…Saini and Choudhary [19] suggested that the relative change in on‐current ( I on ) and device capacitance ( C gg ) is the prime factor to investigate the delay of the circuit. The parasitic capacitance and resistance due to the interconnects has also been considered in the simulation set up as per [24].…”

Section: T Sram Design and Analysismentioning

confidence: 99%

Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal

Nandi

2018

Micro & Nano Letters

View full text Add to dashboard Cite

show abstract

“…Fig. 15 shows the comparison of 10nm SiNW FET based 6T SRAM cell static margins HSNM, RNM and WM at zero stress time (without NBTI) with TCAD SiNW FET [29], FinFET [30] and planar [31] SRAM cell. We see that 10nm SiNW FET based SRAM cell shows better performance compared to other devices due to its better gate control (short channel immunity) and higher I ON /I OFF ratio.…”

Section: Time (S)mentioning

confidence: 99%

“…The HSNM degradation in to configurations is due to asymmetric strength of inverter (two and three wires in PD) formed by NW1, NW2 and weakening of PU (NW1) transistor due to NBTI cause squeezing of upper lobe of butterfly curve. 14nm SiNW TCAD [29] 25nm SOI MOSFET [31] V dd = 0.9 V Voltage (mV)…”

Section: Time (S)mentioning

confidence: 99%

See 1 more Smart Citation

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Prakash

Beniwal²,

Maheshwaram³

et al. 2017

IEEE Trans. Device Mater. Relib.

Self Cite

View full text Add to dashboard Cite

 Abstract-For sub-20nm FinFET and nanowire CMOS devices, NBTI is an important reliability issue, and requires an accurate model to predict device and circuit performance. In this paper, we report well calibrated predictive and scalable compact Verilog-A based compact model, integrated with NBTI model for nanowire (NW) CMOS circuit simulation and design. The stress and recovery NBTI model for Si NW FET is obtained from experimental NW pMOSFETs using range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar MOSFETs. This is attributed to its cylindrical gate structure resulting in enhanced 2-D hydrogen diffusion and stress induced Si/SiO 2 traps. This emphasizes need for evaluating NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, and interface states generation, inverter delay and RO frequency degrades rapidly and saturates in long term 10-year lifetime. Finally, design of SRAM cell employing multi-wire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using appropriate design configuration. This study underscores need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at device and circuit level. Index Terms-CompactModeling, Negative Bias Temperature Instability (NBTI), Stress and Recovery Modeling, Silicon nanowire FET/CMOS, Si NW SRAM.

show abstract