Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Tayal, Shubham; Nandi, Ashutosh

doi:10.1049/mnl.2017.0867

Cited by 12 publications

(3 citation statements)

References 24 publications

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“…GAA MOSFET based on Silicon are considered as the best alternative to the planar MOSFET because of better gate bias control. This will leads to the suppression of various short channel effects [31][32][33][34] As CMOS technology continues to scale, there are different effects arises by doped polysilicon like high resistance, compatibility with high-k gate dielectrics and gate electrode depletion. To overcome this problem, metal gate electrode is introduced.…”

Section: Introductionmentioning

confidence: 99%

Effect of Gate Metal Work-function on Junctionless (JL) Nanowire GAA MOSFET Performance

Angara

Jena

Rooban

2021

Preprint

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Metal gate technology is one of the promising methods used to increase the drain current by increasing the electrostatic controllability. Different metals have different work-function that controls the device performance very closely as gate to source voltage is the basic inputs for these. In this paper the dependency of gate metal work-function on device performance (both for nMOS and pMOS) is extensively investigated. The gate metal work-function value is taken as 4.2eV to 5.1eV with one increment to see the change in potential profile. With this condition, the IOn current, IOff current, threshold voltage, transconductance also calculated for these structures. A decrease value in drain current (1e-6 to 1e-7 A) is observed for both the cases with increase in work-function of gate metal. However, the Off current is getting better (1e-7 to 1e-18 A) while moving towards higher metal work-function values. As a result of which the IOn/IOff ratio increases which leads to higher device performances.

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Section: Introductionmentioning

confidence: 99%

Effect of Gate Metal Work-function on Junctionless (JL) Nanowire GAA MOSFET Performance

Angara

Jena

Rooban

2021

Preprint

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“…In the nanometre regime, the control over channel is no more one‐dimensional in nature. So, for better gate control over the channel, the introduction of multi‐gate and surrounding gate devices came into pictures such as double gate (DG)‐metal oxide semiconductor field‐effect transistors (MOSFETs), tri‐gate fin field effect transistors (FinFETs) and silicon nanowire field‐effect transistors (FETs) [5, 6]. As gate control over the channel increases, it helps in improving subthreshold characteristics such as low

I_{normalOFF}

and SCEs [6].…”

Section: Introductionmentioning

confidence: 99%

Impact of non‐uniformly doped double‐gate junctionless transistor on the performance of 6T‐SRAM bitcell

Panigrahi

Sahu

Lenka

2020

Micro & Nano Letters

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This work substantiates the impact of Gaussian doping on the electrical performance of double gate junctionless field-effect transistor (DG-JLFET). To get a better understanding of the influence of non-uniform doping, the device is compared with uniform-doped DG-JLFET with various concentrations. The device is later used to demonstrate its usability in six-transistor static random access memory (6T SRAM) bitcell by studying the performance metrics, i.e. stability noise margin and write delay. A comparison of performance metrics is also given with uniformly doped DG-JLFET-based-6T SRAM. Improvement in static noise margin was observed with Gaussian doping without compromising with write access time.

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“…To abolish these SCEs, multi‐gate devices has been introduced. They have better gate control over channel charge carriers [1–5]. Gate‐all‐around silicon nanowire FETs (GAA‐SNWTs) are one of such novel multigate devices which additionally facilitates the scaling without hampering the device performance [6].…”

Section: Introductionmentioning

confidence: 99%

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective

Gupta

Nandi

2019

IET Circuits, Devices & Systems

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Here, a comprehensive study of the gate-all-around silicon nanowire field effect transistor (FET) (GAA-SNWTs) with source/drain underlap is performed to investigate the influence of air as spacer dielectric, on analogue/RF behaviour of the device. Parasitic capacitances in nanoscale devices contribute a dominating role in overall device capacitances. Introducing air as spacer dielectric (ε SP) in source/drain underlap region, device parasitic capacitances deteriorates, which improves the overall capacitances. Thus, the analogue/RF figure-of-merit (FOM) of the device enhances, rendering the device suitable for low-power high-frequency operations. For targeting low power applications, FOMs are elicited at 10 μA/ μm. It is perceived that intrinsic gain of the device is almost unaltered for distinct spacer dielectric (Si 3 N 4 and air). Frequencies like cutoff frequency (f T) and maximum oscillation frequency (f MAX) of air spacer dielectric-based underlap GAA-SNWTs are enhanced by 2.92 times and 3.11 times, respectively, when contrasted by the Si 3 N 4 spacer-based GAA-SNWTs. This results in higher percentage improvement in RF-FOM in terms of transconductance frequency product (TFP), gain-frequency product (GFP), and gain transconductance frequency product (GTFP).

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Enhancing the delay performance of junctionless silicon nanotube based 6T SRAM

Cited by 12 publications

References 24 publications

Effect of Gate Metal Work-function on Junctionless (JL) Nanowire GAA MOSFET Performance

Effect of Gate Metal Work-function on Junctionless (JL) Nanowire GAA MOSFET Performance

Impact of non‐uniformly doped double‐gate junctionless transistor on the performance of 6T‐SRAM bitcell

Effect of air spacer in underlap GAA nanowire: an analogue/RF perspective

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