Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

Maheshwaram, Satish; Manhas, S. K.; Kaushal, Gaurav; Bulusu, Anand; Singh, Navab

doi:10.1109/led.2011.2157076

Cited by 39 publications

(15 citation statements)

References 9 publications

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“…Comparing vGAAFETs with hGAAFETs and FinFETs, it was reported that vGAAFETs achieves significant reduction of parasitic capacitance and wirelength [ 59 ]. A design of buried interconnects for vGAAFETs was proposed as shown in Figure 9 [ 60 ]. In the design, the lateral interconnects, M1-V and M3-V, for both Source and Drain sides were used.…”

Section: This Part Covers the Transistor Designs To The End Of Tecmentioning

confidence: 99%

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State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today’s transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore’s law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

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Section: This Part Covers the Transistor Designs To The End Of Tecmentioning

confidence: 99%

“…Another advantage of vGAAFETs is that it can realize multi-layer vertical stacking, thereby further reducing the area of standard cells. In the simulation of Satish Maheshwaram et al [ 60 ], two-layer stacked vGAAFETs can reduce the area by 20% compared to single-layer CMOS.…”

Section: This Part Covers the Transistor Designs To The End Of Tecmentioning

confidence: 99%

State of the Art and Future Perspectives in Advanced CMOS Technology

et al. 2020

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“…Also, design technology co-optimization (DTCO) on pitch scaling and patterning approaches its physical and technical cliff in 2D process technology. To overcome these problems by shifting to a 3-D design paradigm, a new transistor structure called vertical gate-all-around (GAA) nanowire FET (VFET) has emerged as a promising candidate for sub-5nm nodes [1]- [4]. Also, the authors of [5] and [6] have demonstrated the feasibility of stacked logic transistors along the vertical nanowire.…”

Section: Introductionmentioning

confidence: 99%

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Lee

Kang

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable PPAC (power, performance, area, and cost) benefits. In this paper, we propose a novel SMT (Satisfiability Modulo Theories)-based many-tier VFET standard cell (SDC) synthesis framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint and a dummy gate control scheme to capture the unique VFET cell architecture. Moreover, we present efficient objectives to improve pin-accessibility and reduce the use of vertical routing, which has high resistance. Compared to the conventional sequential P&R approach, our concurrent P&R achieves a 15.2% smaller cell area on average for 2tier VFET. Throughout the extensive exploration for many-tier VFET configurations up to 4-tier, we show that the 4-tier VFET respectively achieves 50.1% and 27.9% of average area reduction on chip-level and block-level, over 4.5T GAAFET.

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“…Devices with the GAA structure showed better electric transport performance thanks to their superior electrostatic integrity. Maheshwaram et al reported that, by using the vertical GAA Si nanowire MOSFETs (NWFETs) instead of the FinFET, the ring oscillator delay and the power consumption are improved by 33% and 45%, respectively [6]. In addition, nanowires based on different materials and geometry cross-section can be used as transducers, sensors or photovoltaic devices [7,8,9,10].…”

Section: Introductionmentioning

confidence: 99%

Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs

Lee¹,

Badami²,

Carrillo-Nuñez³

et al. 2018

Micromachines

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Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on SixGe1−x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from sp3d5s∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.

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Vertical Silicon Nanowire Gate-All-Around Field Effect Transistor Based Nanoscale CMOS

Cited by 39 publications

References 9 publications

State of the Art and Future Perspectives in Advanced CMOS Technology

State of the Art and Future Perspectives in Advanced CMOS Technology

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs

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