Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

Maheshwaram, Satish; Manhas, S. K.; Kaushal, Gaurav; Bulusu, Anand; Singh, Navab

doi:10.1109/ted.2013.2272651

Cited by 30 publications

(15 citation statements)

References 26 publications

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“…Although it is out of the scope of this paper, this approach can be generalized to other architectures such as nanowires [28], [29] or FinFET [30], [31]. Finally, this model is simple and efficient enough for implementation in the MASTAR platform.…”

Section: Discussionmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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In this paper, the main MOSFET parasitic capacitances of planar devices (i.e., bulk, Fully depleted silicon-on-insulator (FDSOI), and planar double gate) are computed using two successive conformal mapping transforms. First, the structure is mapped to the real axis of the complex plane, and then the second transform, deduced directly from the Schwarz-Christoffel theorem, reduces the capacitance to the trivial parallel electrodes case. This second step involves elliptic integrals, which provide a generic expression for all parasitic capacitances. This method is later compared against other models based on conformal mapping. Finally, the results are validated with finite-element method simulations of the inner and outer fringe capacitances in different architectures, including metallic contacts and raised and faceted junctions.Index Terms-CMOS, compact model, conformal mapping, electrostatic, elliptic integrals, Model for Assessment of CMOS Technologies and Roadmaps (MASTAR), MOSFET, parasitic capacitance, roadmap.

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Section: Discussionmentioning

confidence: 99%

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Hiblot

Rafhay

Bœuf

et al. 2015

IEEE Trans. Electron Devices

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“…When the top tip of vertical pillar serves as the source, the Ion is about 30% larger than the case where substrate side serves as the source, which could be due to low doping on the bottom side caused by the shadowing effect [2]. However, the results in [16] show that a two-stage inverter delay is nearly 50% higher when top tip of vertical pillar serves as the source because of the increased series resistance and load capacitance. Therefore, the electrode asymmetry and parasitics are important considerations for circuit design using VGAA.…”

Section: A Introduction To Vertical Fetsmentioning

confidence: 95%

Efficient Layout Generation and Design Evaluation of Vertical Channel Devices

Wang

Gupta

2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Vertical gate-all-around (VGAA) has been shown to be one of the most promising devices for the scaling beyond 10nm for its reduced delay, large driving current, and good gate control. Moreover, emerging devices such as heterojunction tunneling FETs are more amenable to vertical fabrication. However, past studies of vertical channel devices focused more on regular memory architectures and simple standard cells like inverter. Since naive migration of regular FinFET layouts to vertical FETs yields little benefits, we identify several vertical efficient layout structures and propose novel layout generation heuristics for vertical channel devices. We also compare VGAA with symmetric and asymmetric source/drain architectures. The layout efficiencies of several VGAA structures, vertical double gate (VDG), lateral gate-all-around (LGAA), and FinFET are presented in our experiments. We observe that even though most vertical channel standard cells have more diffusion gaps than lateral cells do, they still benefit from vertical architectures in area because of the elimination of diffusion contacts. For asymmetric architectures, the area is larger than symmetric architectures because of the extra diffusion gaps needed, but our experiments indicate that for both symmetric and asymmetric architectures, vertical channel devices are likely to have a density advantage over lateral channel devices assuming that current drive strengths of both are similar.

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“…During the output-fall transition to 0.5V DD , the transistor P2 remains ON while N2 switches from OFF to ON. As a result, the OFF to ON ratio of 0.25: 0.75 [20][21][22] is utilized to calculate C IN2 (3).…”

Section: Cmos Inverter Performance Analysismentioning

confidence: 99%

“…The VS superior NW performance is due to its gate-all-around (GAA) based architecture. Recent research [1][2][3] has shown that VS-NWs are capable of balancing outstanding low off-state and high on-state properties. However, none of these studies have taken into account the VS-NW structure's spacer optimization, which is an unavoidable for sub-10 nm nodes for better gate controllability [4].…”

Section: Introductionmentioning

confidence: 99%

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

Sreenivasulu

Narendar

2022

Silicon

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The main aim of this work is to study the effect of symmetric and asymmetric spacer length variations towards source and drain on n-channel SOI JL vertically stacked (VS) nanowire (NW) FET at 10 nm gate length (L G ). Spacer length is proved to be one of the stringent metrics in deciding device performance along with width, height and aspect ratio (AR). The physical variants in this work are symmetric spacer length (L SD ), source side spacer length (L S ) and drain side spacer length (L D ). The simulation results give highest I ON /I OFF ratio with L D variation compared to L S and L SD , whereas latter two variations have similar effect on I ON /I OFF ratio. At 25 nm (2.5 × L G ) of L D , the device gives appreciable ON current with the highest I ON /I OFF ratio (2.19 × 10 8 ) with optimum subthreshold slope (SS) and ensures low power and high switching drivability. Moreover, it is noticed that among optimal values of L S and L D , the device I ON /I OFF ratio has an improvement of 22.69% as compared to other variations. Moreover, the effect of various spacer dielectrics on optimized device is also investigated. Finally, the CMOS inverter circuit analysis is performed on the optimized symmetric and asymmetric spacer lengths.

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Vertical Nanowire CMOS Parasitic Modeling and its Performance Analysis

Cited by 30 publications

References 26 publications

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Refined Conformal Mapping Model for MOSFET Parasitic Capacitances Based on Elliptic Integrals

Efficient Layout Generation and Design Evaluation of Vertical Channel Devices

Circuit Analysis and Optimization of GAA Nanowire FET Towards Low Power and High Switching

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