Impact of series resistance on Si nanowire MOSFET performance

Kaushal, Gaurav; Manhas, S. K.; Maheshwaram, Satish; Dasgupta, S.

doi:10.1007/s10825-013-0449-8

Cited by 14 publications

(6 citation statements)

References 18 publications

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“…In contrast, the V th of WSND TFET slightly increases with the different thickness of the drain side, because the flow of tunneling electrons generated at the source junction is disturbed by the high series resistance of the narrow drain side. 32) Compared with the conventional TFET, the TFET with asymmetric channel thickness has slightly smaller I on [Figs. 6(a When SiO 2 is used as the gate material, the NSWD TFET with 8 nm of narrow source can reduce the SS value by 11 mV=dec (42 → 31 mV=dec).…”

Section: Resultsmentioning

confidence: 99%

“…As the thickness of the source side decreases, the V th is reduced from 0.7 to 0.67 V (by 4.2%) in NSWD TFETs with HfO 2 insulator, while it drops from 0.94 to 0.84 V (by 11%) in NSWD TFETs with SiO 2 insulator. In contrast, the V th of WSND TFET slightly increases with the different thickness of the drain side, because the flow of tunneling electrons generated at the source junction is disturbed by the high series resistance of the narrow drain side 32). Compared with the conventional TFET, the TFET with asymmetric channel thickness has slightly smaller I on [Figs.6(a) and 6(b)], because the NSWD and the WSND TFETs suffer from the volume limitation of the narrow source and high series resistance of the narrow drain side.…”

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confidence: 95%

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Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

Kim

Meyyappan

et al. 2017

Jpn. J. Appl. Phys.

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Effects of using asymmetric channel thickness in tunneling field-effect transistors (TFET) are investigated in sub-50 nm channel regime using two-dimensional (2D) simulations. As the thickness of the source side becomes narrower in narrow-source wide-drain (NSWD) TFETs, the threshold voltage (Vth) and the subthreshold swing (SS) decrease due to enhanced gate controllability of the source side. The narrow source thickness can make the band-to-band tunneling (BTBT) distance shorter and induce much higher electric field near the source junction at the on-state condition. In contrast, in a TFET with wide-source narrow-drain (WSND), the SS shows almost constant values and the Vth slightly increases with narrowing thickness of the drain side. In addition, the ambipolar current can rapidly become larger with smaller thickness on the drain side because of the shorter BTBT distance and the higher electric-field at the drain junction. The on-current of the asymmetric channel TFET is lower than that of conventional TFETs due to the volume limitation of the NSWD TFET and high series resistance of the WSND TFET. The on-current is almost determined by the channel thickness of the source side.

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Section: Resultsmentioning

confidence: 99%

mentioning

confidence: 95%

Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

Kim

Meyyappan

et al. 2017

Jpn. J. Appl. Phys.

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“…8, become major issue and degrade the device performance. Therefore, our compact model incorporates TCAD calibrated parasitic resistance [18] and geometric dependent parasitic capacitance [19] model for circuit simulation to make the analysis accurate, predictive and realistic. For the accuracy of developed compact model, it is calibrated with both experimental and TCAD data.…”

Section: Integrated Nbti Model For Nw Circuit Simulationmentioning

confidence: 99%

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Prakash

Beniwal²,

Maheshwaram³

et al. 2017

IEEE Trans. Device Mater. Relib.

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 Abstract-For sub-20nm FinFET and nanowire CMOS devices, NBTI is an important reliability issue, and requires an accurate model to predict device and circuit performance. In this paper, we report well calibrated predictive and scalable compact Verilog-A based compact model, integrated with NBTI model for nanowire (NW) CMOS circuit simulation and design. The stress and recovery NBTI model for Si NW FET is obtained from experimental NW pMOSFETs using range of stress voltage, time, and temperature. It is found that NBTI is more pronounced in SiNW FET compared to FinFET and planar MOSFETs. This is attributed to its cylindrical gate structure resulting in enhanced 2-D hydrogen diffusion and stress induced Si/SiO 2 traps. This emphasizes need for evaluating NW circuit performance. Using the developed model, the impact of NBTI on NW CMOS circuits: inverter, 13-stage ring oscillator (RO), and 6T SRAM performance is analyzed. It is found that initially (for 1 year of life time) due to fast trapping, and interface states generation, inverter delay and RO frequency degrades rapidly and saturates in long term 10-year lifetime. Finally, design of SRAM cell employing multi-wire sizing technique is investigated. We show that the NBTI impact on SRAM cells is configuration dependent, which can be reduced by using appropriate design configuration. This study underscores need for predictive modeling and mitigation of NBTI degradation in NW CMOS, both at device and circuit level. Index Terms-CompactModeling, Negative Bias Temperature Instability (NBTI), Stress and Recovery Modeling, Silicon nanowire FET/CMOS, Si NW SRAM.

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“…R SD and its components are calculated using a compact model and compared with R SD extracted by the Y-function technique 24,25) to ensure the accuracy of the R SD model. calculated R SD is comparable to the extracted R SD for all high-κ materials; thus, the compact model used in this work is suitable for explaining the TCAD simulation data (to be shown in Fig.…”

Section: Si-nwfet Structure and Parasitic Rc Extractionmentioning

confidence: 99%

“…To accurately analyze AC performance (CV=I, f T ), R SD is calculated using an analytic model and found to agree with value extracted by the Y-function technique. 24,25) C para is also extracted by an extrapolation method customized for NWFETs. 26) On the basis of the results of this comprehensive analysis, design guidelines to optimize the DC=AC performance of GAA NWFETs are suggested for the sub-10 nm technology node.…”

Section: Introductionmentioning

confidence: 99%

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

Hong¹,

Lee²,

Kim³

et al. 2015

Jpn. J. Appl. Phys.

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In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.

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Impact of series resistance on Si nanowire MOSFET performance

Cited by 14 publications

References 18 publications

Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

Electrical characteristics of tunneling field-effect transistors with asymmetric channel thickness

Compact NBTI Reliability Modeling in Si Nanowire MOSFETs and Effect in Circuits

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

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