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This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/ √ Hz at 6.8 mW.

This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2 .

• with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.

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In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...