A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications

Harikumar, Prakash; Wikner, J. Jacob; Alvandpour, Atila

doi:10.1109/tcsii.2016.2531099

Cited by 19 publications

(6 citation statements)

References 10 publications

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“…Usually, the power density of the ambient power source is very small, 10−500nW/mm 3 g 2 for vibration energy [5,6]. As a result, ultra-low power consumption is a crucial point for passive WSN electronics [7].…”

Section: Introductionmentioning

confidence: 99%

“…Ref. [7] proposed a sub-nanowatt SAR ADC using a supply voltage of 0.4 V. Additionally, minimum-sized high-V th (HVT) devices can be used to minimize leakage current. On the other hand, a capacitive digital-to-analog converter (DAC) is the significant power consumption of a SAR ADC, mainly determined by the switching scheme and the total capacitance.…”

Section: Introductionmentioning

confidence: 99%

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A nanowatt noise-shaping SAR ADC for passive wireless sensor node application

Yang

Zhang

2022

IEICE Electron. Express

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This paper presents a novel first-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) for passive wireless sensor node application. To decrease dynamic power consumption, one-side switching instead (OSSI) method and higher-bit switching instead (HBSI) method are adopted in our proposed noise-shaping architecture. Dynamic SAR logic and dynamic comparator are used to further reduce power consumption. In addition, a low supply voltage is applied to this ADC, which can decrease static current leakage. The proposed noiseshaping SAR ADC was fabricated in 0.18 um 1P4M CMOS technology, which occupies an active area of 0.185 mm 2 . The prototype chip consumes 89 nW at 25 kHz sampling rate. The measurement shows 58.2 dB signal to noise and distortion ratio (SNDR) can be achieved.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A nanowatt noise-shaping SAR ADC for passive wireless sensor node application

Yang

Zhang

2022

IEICE Electron. Express

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“…1 Such devices allow banking operations, mail-checking, and travel-booking services, which are user-friendly and easily accessible. Furthermore, wearable devices and modern remote sensors [2][3][4] have drastically changed the study and treatment of medical pathologies, [5][6][7] which can now be remotely monitored and diagnosed. As a consequence, the ever-increasing popularity of smart systems has motivated researchers to develop ultra-low-power (ULP) and ultralow-voltage (ULV) electronic devices.…”

Section: Introductionmentioning

confidence: 99%

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages

Sala

Centurelli

Monsurrò

et al. 2022

Circuit Theory & Apps

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This paper presents a novel topology of ultra-low voltage (ULV) operational transconductance amplifier (OTA), which exploits several design techniques to achieve high efficiency, symmetrical slew rate, good linearity, and robustness in spite of ultra-low voltage operation. Simulations in a commercial 130-nm CMOS technology with 0.3-V supply voltage show the best reported small-signal figure-of-merit among 0.3-V OTAs, with a dc gain of 56.2 dB, a unity-gain frequency of 26.2 kHz over a 150-pF load capacitor, and a power consumption of 139.5 nW. A symmetrical slew rate of about 3.2 V/ms is achieved, and results are consistent under process, supply voltage and temperature variations, and device mismatches.

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“…The emerging applications of SAR ADCs range from biomedical instruments where power consumption is of a great importance [4] to high-speed data links where conversion rate is pivotal [5,6], largely accredited to the full compatibility of SAR ADCs with technology scaling [7]. For example, in the low-power realm, SAR ADCs with kS/s rates and 10-bit resolution dissipate only a few micro watts [8,9,10,11]. In the high-speed realm, a sea of 64 time-interleaved SAR ADCs are capable of achieving 90 GS/s [12].…”

Section: Introductionmentioning

confidence: 99%

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

Lee¹

2021

Preprint

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file:///C:/Users/MWF/Downloads/Lee, Daniel Junehee.The 8-bit digital-to-time converter (DTC) to be used for a time-mode successive-approximation register analog-to-digital converter (SAR ADC) with a minimum power consumption and silicon area is presented. The architecture and the drawbacks of a conventional voltage-mode SAR ADC are discussed. The principle of time-mode circuits and benefits of their applications to mixed-signal circuits are explained. The architecture of a time-mode SAR ADC is presented. The need for an area and power-efficient DTC to be used for a time-mode SAR ADC is discussed. The principle of a DTC is explained and prior works on a DTC are reviewed. The principle of a phase interpolator (PI), to be used for a DTC, is explained and prior works on digital PIs are reviewed. The design of the proposed DTC is presented. Each block of the proposed DTC is explained using schematic and layout views. Optimal slope of the input of the PI and the condition for linear phase interpolation are investigated. Simulation results of the proposed DTC designed in TSMC 65 nm 1.0 V CMOS technology are provided. According to simulation results with BSIM4.4 device models only, the time resolution of 0.33 ps, a maximum operation frequency of 2.53 G Hz, the power consumption of 1.38 mW, and peak differential nonlinearity (DNL) and integral nonlinearity (INL) less than 0.14 least significant bit (LSB) and 0.49 LSB, respectively, for a nominal process (TT) and a temperature condition (27 C°) are achieved.

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A 0.4-V Subnanowatt 8-Bit 1-kS/s SAR ADC in 65-nm CMOS for Wireless Sensor Applications

Cited by 19 publications

References 10 publications

A nanowatt noise-shaping SAR ADC for passive wireless sensor node application

A nanowatt noise-shaping SAR ADC for passive wireless sensor node application

A body‐driven rail‐to‐rail 0.3 V operational transconductance amplifier exploiting current gain stages

A Digital-to-Time Converter for Time-Mode Successive-Approximation Register Analog-to-Digital Converters

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