A nanowatt noise-shaping SAR ADC for passive wireless sensor node application

Abstract

This paper presents a novel first-order noise-shaping successive approximation register (SAR) analog-to-digital converter (ADC) for passive wireless sensor node application. To decrease dynamic power consumption, one-side switching instead (OSSI) method and higher-bit switching instead (HBSI) method are adopted in our proposed noise-shaping architecture. Dynamic SAR logic and dynamic comparator are used to further reduce power consumption. In addition, a low supply voltage is applied to this ADC, which can decrease static current leakage. The proposed noiseshaping SAR ADC was fabricated in 0.18 um 1P4M CMOS technology, which occupies an active area of 0.185 mm 2 . The prototype chip consumes 89 nW at 25 kHz sampling rate. The measurement shows 58.2 dB signal to noise and distortion ratio (SNDR) can be achieved.