This paper presents an analog receiver front-end design (AFE) for capacitive body-coupled digital baseband receiver. The most important theoretical aspects of human body electrical model in the perspective of capacitive body-coupled communication (BCC) have also been discussed and the constraints imposed by gain and input-referred noise on the receiver front-end are derived from digital communication theory. Three different AFE topologies have been designed in ST 40-nm CMOS technology node which is selected to enable easy integration in today's system-on-chip environments. Simulation results show that the best AFE topology consisting of a multi-stage AC-coupled preamplifier followed by a Schmitt trigger achieves 57.6 dB gain with an input referred noise PSD of 4.4 nV/ √ Hz at 6.8 mW.
This paper presents a 15-bit, two-stage pipelined successive approximation register (SAR) analog-to-digital converter (ADC) suitable for low-power, cost-effective sensor readout circuits. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array DAC topology in the second stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. An elaborate power consumption analysis of the entire ADC was performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitor-based DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak SNDR of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8 bits at a sampling frequency of 1 kS/s and provides an FoM of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1 bits upto the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2 .
• with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages.
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