Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS

Harikumar, Prakash; Wikner, J. Jacob

doi:10.1109/iscas.2015.7168617

Cited by 22 publications

(20 citation statements)

References 8 publications

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“…Even with advanced rectifiers, such as the reconfigurable resonant regulating rectifier (R 3 rectifier), the ripple of the rectified voltage can still be measured in tens of mV [ 1 ]. For conventional SAR ADCs adopted in such systems [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ], a dedicated regulator is needed to stabilize the reference voltage against the ADC core. However, the regulator consumes significant power [ 2 , 3 , 4 ].…”

Section: Introductionmentioning

confidence: 99%

“…For conventional SAR ADCs adopted in such systems [ 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ], a dedicated regulator is needed to stabilize the reference voltage against the ADC core. However, the regulator consumes significant power [ 2 , 3 , 4 ]. Besides, decoupling capacitors of a few hundred pF or larger values are needed to maintain the stable operation of the regulator [ 10 ].…”

Section: Introductionmentioning

confidence: 99%

“…In the past, most designs focused on optimizing the power and area of the sub-blocks in the SAR ADC core [ 5 , 6 , 7 , 8 ], while only a few studies aimed to optimize the reference-voltage regulator [ 2 , 3 , 4 , 11 ]. It was found that if the power consumption of the reference-voltage regulator is included, the FOM of ADC degrades from 100 fJ/c-s to 1000 fJ/c-s [ 2 ] or from 25 fJ/c-s to 738 fJ/c-s [ 3 ]. In a previous study [ 4 ], a SAR ADC with energy-efficient reference generation was proposed, in which power saving was realized by applying a duty-cycle technique in the reference generator.…”

Section: Introductionmentioning

confidence: 99%

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A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

Yang

Zhou

Liu

et al. 2018

Sensors

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This paper presents a reference-voltage regulator free successive-approximation-register analog-to-digital converters (SAR ADC) with self-timed pre-charging for wireless-powered implantable medical devices. Assisted by a self-timed pre-charging technique, the proposed SAR ADC eliminates the need for a power-hungry reference-voltage regulator and area-consuming decoupling capacitor while maintaining insensitivity to the supply voltage fluctuation. Fabricated with a 0.18-µm complementary metal–oxide–semiconductor (CMOS) technology, the proposed SAR ADC achieves a Signal To Noise And Distortion Ratio (SNDR) of 53.32 dB operating at 0.8 V with a supply voltage fluctuation of 50 mVpp and consumes a total power of 2.72 µW at a sampling rate of 300 kS/s. Including the self-timed pre-charging circuits, the total figure-of-merit (FOM) is 23.9 fJ/conversion-step and the total area occupied is 0.105 mm2.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 10-Bit 300 kS/s Reference-Voltage Regulator Free SAR ADC for Wireless-Powered Implantable Medical Devices

Yang

Zhou

Liu

et al. 2018

Sensors

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“…The reference voltage can be provided off-chip. However, the parasitic inductors of the bondwires and PCB traces cause ringing on the reference voltage and thus the CDAC output [4]. Adding on-chip decoupling capacitors is one way to mitigate the ringing effect.…”

Section: Introductionmentioning

confidence: 99%

“…The RVBuffer should have rapid settling speed which makes it very power-hungry. The power consumption of the RVBuffer is fifteen times [5] or even twenty-eight times [4] as much as that of the SAR ADC core. The Walden FoM increases dramatically when considering the RVBuffer.…”

Section: Introductionmentioning

confidence: 99%

A 700-MS/s 6-bit SAR ADC with partially active reference voltage buffer

Zhao

Yang

2018

IEICE Electron. Express

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This paper presents a 700-MS/s 6-bit SAR ADC with a novel on-chip reference voltage buffer in a 40-nm CMOS Low-Leakage (LL) process. The reference voltage buffer is partially active depending on the operation state of the SAR ADC. The large driving current is provided only when the Capacitive Digital-to-Analog Converter (CDAC) is settling. This approach achieves 42% power reduction for the reference voltage buffer, which helps to improve the Figure-

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