Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

Aamir, Syed Ahmed; Harikumar, Prakash; Wikner, J. Jacob

doi:10.1109/iscas.2013.6571860

Cited by 13 publications

(8 citation statements)

References 8 publications

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“…The monitored output voltage is multiplexed from among the membrane potential or incoming synaptic activity at any of the two synaptic input lines. The Opamp designed for the buffer is a two-stage amplifier with split-length indirect compensation [54], [55] and is shown in Fig. 1f.…”

Section: Analog Input/outputmentioning

confidence: 99%

An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture

Aamir

Stradmann

Müller

et al. 2018

IEEE Trans. Circuits Syst. I

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We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaleddown prototype HICANN-DLS chip. Designed as continuoustime circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration and measurement results from individual subcircuits across multiple dies. The circuit dynamics match with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing. I . I N T R O D U C T I O NT HE architecture of digital microprocessors is fundamentally different from that of the central nervous system. While the brain is a massively parallel structure of neurons interconnected through synapses [1], microprocessors are mostly based on a von Neumann architecture [2], [3] with logic gates as the elementary primitives. The human brain consumes only approximately 20 W [4], while its performance as a generalpurpose problem solver is still unmatched by any computer algorithm.Taking inspiration from this biological feat, neuromorphic architectures not only adopt a non-von Neumann architecture by collocating memory close to the computational element, but also introduce massive parallelism, high energy efficiency, reconfigurability, fault tolerance, and integrate computational *Both authors contributed equally to this work.

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Section: Analog Input/outputmentioning

confidence: 99%

An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture

Aamir

Stradmann

Müller

et al. 2018

IEEE Trans. Circuits Syst. I

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“…In the proposed technique, the feedback of C m1 is through cascode g mc which can also be defined as an indirect compensation [6]. It helps simplify the circuit and provides better frequency response [7].…”

Section: A Structurementioning

confidence: 99%

Cascode and transconductance with capacitances feedback compensation for multistage amplifiers driving no load and 1nF capacitive load

Zhang

Cai

Chen

et al. 2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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A cascode and transconductance with capacitances feedback compensation (CTCFC) for multistage amplifiers is proposed in this paper. By adding a transconductance with capacitor feedback across the output stage, the shorting effect of this capacitor is eliminated, which enlarges the gain at higher frequency region. This capacitor can also help stabilize no load configuration. The other compensation capacitor through cascode from the output to the first stage simplifies the circuit and provides zeros to further increase the bandwidth. The proposed technique has been verified by an implementation in a 0.6µm CMOS process. The gain-bandwidth product (GBW) is 3.6MHz under a capacitive load of 1nF. The slew rate is 2.6V/µs and the current consumption is 88µA which shows an improvement in IFOML performance.Keywords-cascode and transconductance with capacitances feedback compensation; multistage amplifier; large capacitive load or no load

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“…In all these works, the objective is to achieve sufficient PM and GBW with low values of compensation capacitance such that power efficiency is enhanced. Paper B [36] compares the NMCNR and reversed nested indirect compensation (RNIC) schemes employed on three-stage and four-stage amplifiers.…”

Section: Nested Miller Compensation For Three-stage Otasmentioning

confidence: 99%

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

Harikumar

2014

Linköping Studies in Science and Technology. Thesis

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In today's system-on-chip (SoC) implementations, power consumption is a key performance specification. The proliferation of mobile communication devices and distributed wireless sensor networks has necessitated the development of power-efficient analog, radio-frequency (RF), and digital integrated circuits. The rapid scaling of CMOS technology nodes presents opportunities and challenges. Benefits accrue in terms of integration density and higher switching speeds for the digital logic. However, the concomitant reduction in supply voltage and reduced gain of transistors pose obstacles to the design of highperformance analog and mixed-signal circuits such as analog front-ends (AFEs) and data converters.To achieve high DC gain, multistage amplifiers are becoming necessary in AFEs and analog-to-digital converters (ADCs) implemented in the latest CMOS process nodes. This thesis includes the design of multistage amplifiers in 40 nm and 65 nm CMOS processes. An AFE for capacitive body-coupled communication is presented with transistor schematic level results in 40 nm CMOS. The AFE consists of a cascade of amplifiers to boost the received signal followed by a Schmitt trigger which provides digital signal levels at the output. Low noise and reduced power consumption are the important performance criteria for the AFE. A two-stage, single-ended amplifier incorporating indirect compensation using split-length transistors has been designed. The compensation technique does not require the nulling resistor used in traditional Miller compensation. The AFE consisting of a cascade of three amplifiers achieves 57.6 dB DC gain with an input-referred noise power spectral density (PSD) of 4.4 nV/ √ Hz while consuming 6.8 mW.Numerous compensation schemes have been proposed in the literature for multistage amplifiers. Most of these works investigate frequency compensation of amplifiers which drive large capacitive loads and require low unity-gain frequency. In this thesis, the frequency compensation schemes for high-speed, lowvoltage multistage CMOS amplifiers driving small capacitive loads have been investigated. Existing compensation schemes such as the nested Miller compensation with nulling resistor (NMCNR) and reversed nested indirect compensation (RNIC) have been applied to four-stage and three-stage amplifiers designed in 40 nm and 65 nm CMOS, respectively. The performance metrics used for comparing the different frequency compensation schemes are the unity gain frequency, phase margin (PM), and total amount of compensation capacitance used. From transistor schematic simulation results, it is concluded that RNIC is more efficient than NMCNR.Successive approximation register (SAR) analog-to-digital converters (ADCs) are becoming increasingly popular in a wide range of applications due to their high power efficiency, design simplicity and scaling-friendly architecture. Singlechannel SAR ADCs have reached high resolutions with sampling rates exceeding 50 MS/s. Time-interleaved SAR ADCs have pushed beyond 1 GS/s with medium r...

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Frequency compensation of high-speed, low-voltage CMOS multistage amplifiers

Cited by 13 publications

References 8 publications

An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture

An Accelerated LIF Neuronal Network Array for a Large-Scale Mixed-Signal Neuromorphic Architecture

Cascode and transconductance with capacitances feedback compensation for multistage amplifiers driving no load and 1nF capacitive load

Building Blocks for Low-Voltage Analog-to-Digital Interfaces

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