A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

This paper presents a 10-bit 50-MS/s subrange successive-approximation register (SAR) analog-to-digital converter (ADC) composed of a 4-bit SAR coarse ADC and a 6-bit SAR fine ADC. In the coarse ADC, multi-comparator SAR architecture is used to reduce the digital logic propagation delay, and a traditional asynchronous SAR ADC with monotonic switching method is used as the fine ADC. With that combination, power dissipation also can be much reduced. Meanwhile, a modified SAR control logic is adopted in the fine ADC to speed up the conversion and other techniques, such as splitting capacitors array, are borrowed to reduce the power consumption. Fabricated with 1P8M 130-nm CMOS technology, the proposed SAR ADC achieves 51.6-dB signal to noise and distortion ratio (SNDR) and consumes 186 μW at 50 MS/s with a 1-V supply, resulting in a figure of merit (FOM) of 12 fJ/conversion-step. The core area is only 0.045 mm2.

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“…Performance comparison with other published SAR ADCs. Parameter Reference [13] Reference [21] Reference [22] Reference [15]…”

Section: -5mentioning

confidence: 99%

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

Mingyuan

Li²,

Yang

et al. 2016

J. Semicond.

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“…It is worth noting that the S/H noise given by kT /C s is significantly impacted by the change in temperature. For the bootstrapped S/H circuit with a C s = 480 fF reported in [13], the simulated output noise over the entire set of process, supply voltage and temperature (PVT) corners is shown in Fig. 2-2.…”

Section: Thermal Noisementioning

confidence: 99%

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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“…10.536/À0.676 LSB. Another study (Harikumar and Wikner, 2015) also adopted hybrid ADC; SAR ADC and preamplifier in their design and attained power less than 1 mW at 50 MS/s with DNL error of 0.3 LSB. Meanwhile, Palomo et al (2012) implemented sub-sampling technique to solve high power consumption issue.…”

Section: Introductionmentioning

confidence: 99%

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

Idros

Aziz

Rajendran

2020

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Purpose The purpose of this paper is to demonstrate the acceptable performance by using the limited input range towards lower open-loop DC gain operational amplifier (op-amp) of an 8-bit pipelined analog-to-digital converter (ADC) for mobile communication application. Design/methodology/approach An op-amp with folded cascode configuration is designed to provide the maximum open-loop DC gain without any gain-boosting technique. The impact of low open-loop DC gain is observed and analysed through the results of pre-, post-layout simulations and measurement of the ADC. The fabrication process technology used is Silterra 0.18-µm CMOS process. The silicon area by the ADC is 1.08 mm2. Findings Measured results show the differential non-linearity (DNL) error, integral non-linearity (INL) error, signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) are within −0.2 to +0.2 LSB, −0.55 LSB for 0.4 Vpp input range, 22 and 27 dB, respectively, with 2 MHz input signal at the rate of 64 MS/s. The static power consumption is 40 mW with a supply voltage of 1.8 V. Originality/value The experimental results of ADC showed that by limiting the input range to ±0.2 V, this ADC is able to give a good reasonable performance. Open-loop DC gain of op-amp plays a critical role in ADC performance. Low open-loop DC gain results in stage-gain error of residue amplifier and, thus, leads to nonlinearity of output code. Nevertheless, lowering the input range enhances the linearity to ±0.2 LSB.

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A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

Cited by 8 publications

References 35 publications

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier

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A 10-bit 50 MS/s SAR ADC in 65 nm CMOS with on-chip reference voltage buffer

Cited by 8 publications

References 35 publications

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

A 1 V 186-μW 50-MS/s 10-bit subrange SAR ADC in 130-nm CMOS process

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

A 1-mm2 CMOS-pipelined ADC with integrated folded cascode operational amplifier

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A 1-mm² CMOS-pipelined ADC with integrated folded cascode operational amplifier