Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump

Harikumar, Prakash; Wikner, J. Jacob

doi:10.1109/norchip.2014.7004703

Cited by 5 publications

(5 citation statements)

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“…Eq. (2.38) indicates that the sub-threshold leakage current depends on the voltage across the switch (V DS ) and further introduces harmonic distortion at the output of the ADC [46]. Leakage reduction can be achieved by using a stack of seriesconnected transistors [44], implementation of high-V th transistors [47], negative body bias [48], negative gate bias [49] or a combination of these solutions.…”

Section: Impact Of Leakagementioning

confidence: 99%

Energy-Efficient Data Converters for Low-Power Sensors

Chen

2017

Linköping Studies in Science and Technology. Dissertations

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Wireless sensor networks (WSNs) are employed in many applications, such as for monitoring bio-potential signals and environmental information. These applications require high-resolution (> 12-bit) analog-to-digital converters (ADCs) at low-sampling rates (several kS/s). Such sensor nodes are usually powered by batteries or energyharvesting sources hence low power consumption is primary for such ADCs. Normally, tens or hundreds of autonomously powered sensor nodes are utilized to capture and transmit data to the central processor. Hence it is profitable to fabricate the relevant electronics, such as the ADCs, in a low-cost standard complementary metal-oxidesemiconductor (CMOS) process. The two-stage pipelined successive approximation register (SAR) ADC has shown to be an energy-efficient architecture for high resolution. This thesis further studies and explores the design limitations of the pipelined SAR ADC for high-resolution and low-speed applications. The first work is a 15-bit, 1 kS/s two-stage pipelined SAR ADC that has been implemented in 0.35-µm CMOS process. The use of aggressive gain reduction in the residue amplifier combined with a suitable capacitive array digital-to-analog converter (DAC) topology in the second-stage simplifies the design of the operational transconductance amplifier (OTA) while eliminating excessive capacitive load and consequent power consumption. A comprehensive power consumption analysis of the entire ADC is performed to determine the number of bits in each stage of the pipeline. Choice of a segmented capacitive array DAC and attenuation capacitorbased DAC for the first and second stages respectively enable significant reduction in power consumption and area. Fabricated in a low-cost 0.35-µm CMOS process, the prototype ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 78.9 dB corresponding to an effective number of bits (ENOB) of 12.8-bit at a sampling frequency of 1 kS/s and provides a Schreier figure-of-merit (FoM) of 157.6 dB. Without any form of calibration, the ADC maintains an ENOB > 12.1-bit up to the Nyquist bandwidth of 500 Hz while consuming 6.7 µW. Core area of the ADC is 0.679 mm 2. The second work is a 14-bit, tunable bandwidth two-stage pipelined SAR ADC which is suitable for low-power, cost-effective sensor readout circuits. To overcome the high open-loop DC gain requirement of the OTA in the gain-stage, a 3-stage x

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Section: Impact Of Leakagementioning

confidence: 99%

Energy-Efficient Data Converters for Low-Power Sensors

Chen

2017

Linköping Studies in Science and Technology. Dissertations

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“…2-4. The TG switch uses standard-V T H devices with (W/L) N = (1.2 µm/.12 µm) and (W/L) P = (2.4 µm/.12 µm) For ultra-low-voltage applications, conventional bootstrapping [16] proves inadequate to overcome this limitation, and hence doublebootstrapping [17] or cascade of charge pumps [18][19][20] are often employed. It is worth noting that there exists a trade-off between the number of charge pump stages in the cascade and the deterioration in voltage boosting due to parasitic capacitances [19].…”

Section: Tracking Bandwidthmentioning

confidence: 99%

“…Major constituents of gate leakage are gate oxide tunneling and injection of hot carriers from substrate to the gate oxide [21]. In analog and mixed-signal circuits working at very low frequencies, the leakage power forms a significant portion of the total power consumption.The sub-threshold leakage current depends on the voltage across the switch as seen in (2.10) and hence causes harmonic distortion at the ADC output [20,22]. This problem is particularly acute in SAR ADCs with low sampling rates.…”

Section: Impact Of Leakagementioning

confidence: 99%

“…However, bottom-plate input sampling technique is not suitable for ultra-low voltage SAR ADCs since a large number of charge-pump based switches will be required. Leakage-suppression is achieved in top-plate S/H circuits using device-stacking [22], employment of high-V T H devices [20], negative body bias [19], negative gate bias [23] or a combination of these techniques. For the MOS transistors, the subthreshold leakage current increases with temperature while the threshold voltage reduces with temperature.…”

Section: Impact Of Leakagementioning

confidence: 99%

“…To achieve sufficiently low R ON for the TG switch, a two-stage charge pump as shown in Fig. 3-2 was implemented to generate the boosted control voltage for the TG switch [20]. Based on charge conservation analysis and ignoring charge sharing on parasitic capacitance as well as leakage, it can be found that the output node SA in the second stage is at 3V DD and node SAb goes to 0 V when Clk in is HIGH.…”

Section: Input Sampling Switchmentioning

confidence: 99%

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Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Harikumar¹

2016

Linköping Studies in Science and Technology. Dissertations

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Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these distributed WSNs are often low, ultra-low-power ADCs with low sampling rates are required. The advent of new wireless standards with ever-increasing data rates and bandwidth necessitates ADCs capable of meeting the demands. Wireless standards such as GSM, GPRS, LTE and WLAN require ADCs with several tens of MS/s speed and moderate resolution (8-10 bits). Since these ADCs are incorporated into battery-powered portable devices such as cellphones and tablets, low power consumption for the ADCs is essential.The first contribution is an ultra-low-power 8-bit, 1 kS/s successive approximation register (SAR) ADC that has been designed and fabricated in a 65-nm CMOS process. The target application for the ADC is an autonomously-powered soil-moisture sensor node. At V DD = 0.4 V, the ADC consumes 717 pW and achieves an FoM = 3.19 fJ/conv-step while meeting the targeted dynamic and static performance. The 8-bit ADC features a leakage-suppressed S/H circuit with boosted control voltage which achieves > 9-bit linearity. A binary-weighted capacitive array digital-to-analog converter (DAC) is employed with a very low, custom-designed unit capacitor of 1.9 fF. Consequently the area of the ADC and power consumption are reduced. The ADC achieves an ENOB of 7.81 bits at near-Nyquist input frequency. The core area occupied by the ADC is only 0.0126 mm 2 .The second contribution is a 1.2 V, 10 bit, 50 MS/s SAR ADC designed and implemented in 65 nm CMOS aimed at communication applications. For medium-tohigh sampling rates, the DAC reference settling poses a speed bottleneck in chargeredistribution SAR ADCs due to the ringing associated with the parasitic inductances. Although SAR ADCs have been the subject of intense research in recent years, scant attention has been laid on the design of high-performance on-chip reference voltage buffers. The estimation of important design parameters of the buffer as well iv critical specifications such as power-supply sensitivity, output noise, offset, settling time and stability have been elaborated upon in this dissertation. The implemented buffer consists of a two-stage operational transconductance amplifier (OTA) combined with replica source-follower (SF) stages. The 10-bit SAR ADC utilizes split-array capacitive DACs to reduce area and power consumption. In post-layout simulation which includes the entire pad frame and associated parasitics, the ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the ...

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Bootstrapping techniques for energy-efficient successive approximation ADC

Yuan

2022

Analog Integr Circ Sig Process

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Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump

Cited by 5 publications

References 8 publications

Energy-Efficient Data Converters for Low-Power Sensors

Energy-Efficient Data Converters for Low-Power Sensors

Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

Bootstrapping techniques for energy-efficient successive approximation ADC

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