This paper presents the latest 1.2kV-2.2kV SiC MOSFETs designed to maximize SiC device benefits for highpower, medium voltage power conversion applications. 1.2kV, 1.7kV and 2.2kV devices with die size of 4.5mm x 4.5mm were fabricated, exhibiting room temperature on-resistances of 34mOhm, 39mOhm and 41mOhm, respectively. The ability to safely withstand single-pulse avalanche energies of over 17J/cm 2 is demonstrated. Next, the 1.7kV SiC MOSFETs were used to fabricate half-bridge power modules. The module typical onresistance was 7mOhm at Tj=25 o C and 11mOhm at 150 o C. The module exhibits 9mJ turn-on and 14mJ turn-off losses at Vds=900V, Id=400A. Validation of GE's SiC MOSFET performance advantages was done through continuous buckboost operation with three 1.7kV modules per phase leg exhibiting 99.4% efficiency. Device ruggedness and tolerance to terrestrial cosmic radiation was evaluated. Experimental results show that higher voltage devices (2.2kV and 3.3kV) are more susceptible to cosmic radiation, requiring up to 45% derating in order to achieve module failure rate of 100 FIT, while 1.2kV MOSFETs require only 25% derating to deliver similar FIT rate. Finally, the feasibility of medium voltage power conversion based on series connected 1.2kV SiC MOSFETs with body diode is demonstrated.

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This work discusses the possibility of using SiC MOSFET body diode in switching power conversion applications, focusing on performance and reliability aspects.

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The early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.