Mechanisms of Stacking Fault Growth in SiC PiN Diodes

Abstract

The early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.

Nucleation of in-grown stacking faults and dislocation half-loops in 4H-SiC epitaxy

“…These SFs are formed by the motion of one of the partial dislocations comprising a perfect basal plane dislocation (BPD). 13 Therefore, there is an increasing interest in growing 4H-SiC epilayers on substrates polished with an off-angle lower than 8 off-cut. A lower off-angle leads to a decrease in the number of basal planes intersecting the substrate/epilayer interface and increases the probability of BPDs converting to threading edge dislocations (TEDs) instead of propagating into the epilayer.…”

“…A lower off-angle leads to a decrease in the number of basal planes intersecting the substrate/epilayer interface and increases the probability of BPDs converting to threading edge dislocations (TEDs) instead of propagating into the epilayer. 13,14 A lower off-angle will also lead to lower material losses when wafers are sliced from boules.…”

H2 etching and epitaxial growth on 4H-SiC boule domes

“…One of the main concerns in SiC is basal plane dislocations (BPD), which cause devices to fail [1]. Many researchers have strived to reduce these dislocations with some progress by varying pre-growth treatments [2] and growth parameters [3]; however, more efforts are needed to overcome the issue.…”

“…Conventional 4H-SiC growth takes place on 8° off-axis substrate, which results in smooth morphology due to step flow growth [4]. However, it is known that growth on off-axis substrates allows many BPDs to propagate into the subsequent epilayers which comprise of the active region of the device [1]. One way to reduce propagation of these dislocations is to grow on low off-axis material.…”

Structural characterization of double stacking faults induced by cantilever bending in nitrogen-doped 4H-SiC

“…However, despite the high crystalline perfection of the wafers now available, the use of SiC still remains restricted because of the expansion of device-killer stacking faults (SFs) dragged by Shockley partial dislocations under forward biasing of bipolar devices [1][2][3][4][5][6][7][8][9][10][11]. In addition, the formation of double stacking faults (DSFs) bound by two Shockley partial dislocations during oxidation [12], annealing [13][14][15] or hightemperature processing [16] of highly nitrogen-doped 4H-SiC (10 18 -10 19 cm À3 ) has also been reported.…”