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A new compact model for monolithic transformers on silicon substrates is presented. The new lumped-element equivalent circuit model employs transformer loops to represent skin and proximity effects including eddy current loss in the windings of the transformer. In addition to the self-resistances and self-inductances of the windings, the effects of the frequency-dependent mutual resistance and mutual inductance are included in the model. The new compact model has been applied to a stacked transformer on a 10-cm CMOS substrate. The extracted circuit model shows very good agreement with data obtained by full-wave electromagnetic simulation and measurement over the frequency range of 0.1-10 GHz.

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Abstract-Precision electrical trimming of stacked Si/SiGe polycrystalline resistors available from the extrinsic base structure of a SiGe BiCMOS technology has been demonstrated for the first time. It is shown that pulse current trimming techniques can be used to trim the poly-SiGe resistors by up to 50% from their original values with accuracy better than 0.5%. The temperature coefficient of resistance (TCR) is shown to be linearly proportional to the percent change in electrically trimmed poly-SiGe resistance. Finally, we demonstrate resistance cycling using an electrical trim/recovery sequence, indicating that the technique is reversible and is governed by dopant segregation/diffusion mechanisms. The results are consistent with those obtained on conventional polysilicon resistors suggesting that the introduction of a strained SiGe layer does not adversely affect the electrical trim properties of these resistors.

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