CoSi/sub 2/ integrated fuses on poly silicon for low voltage 0.18 μm CMOS applications

Kalnitsky, A.; Saadat, Irfan; Bergemont, A.; Francis, P.

doi:10.1109/iedm.1999.824263

Cited by 17 publications

(13 citation statements)

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“…Recently, a number of programmable fuses that are amenable to implementation on a standard CMOS process have been developed [30,31]. They allow IC device level traceability, serial numbers, redundancy and also allow SRAM timing to be programmed into an IC at test [32].…”

Section: Article In Pressmentioning

confidence: 99%

Reducing process variation impact on replica-timed static random access memory sense timing

2009

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Section: Article In Pressmentioning

confidence: 99%

Reducing process variation impact on replica-timed static random access memory sense timing

2009

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“…This is a gate electrode stack that does not deviate from the typical transistor. Silicided polysilicon gate stacks are widely used in the industry and are reliable elements [4,5,6]. � ISO,OOO fuses were pre-programmed and stressed from each sample, and � IS0,000 fuses were left un-programmed.…”

Section: Introductionmentioning

confidence: 99%

“…the fuse neck, leaving behind a highly resistive polysilicon denuded zone.The denuded polysilicon becomes more resistive by self heating and grain recrystallization, resulting in a stable, high resistance programmed state.Kalnistky[6] describedan E-Fuse similar to the type A design, in which the underlying polysilicon was intrinsic. The use of intrinsic polysilicon requires a prohibitively large transistor aspect ratio in relation to the E-Fuse to maintain adequate current flow during the programming operation.…”

mentioning

confidence: 98%

Reliability, design qualification, and prognostic opportunity of in die E-Fuse

Tonti

2011

2011 IEEE Conference on Prognostics and Health Management

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Sub Micron CMOS features are attractive for Electrical Fuse (E-Fuse) repair options in VLSI designs. E-Fuse implementations as contrasted to laser fuses provide large density advantages over laser fusing and allows for the repair or customization of packaged die. This provides product yield and optimization benefits [1,2). Laser fusing typically requires "keep out" design rules such that fuse neighbors are not unintentionally programmed from a misaligned laser source. Additionally laser fuses typically require a protective cavity to act as a programming debris reservoir.These reasons as well as improving upon the fuse repair solutions required to manage reliability and yield of large die [3) are the major driving forces for providing E-Fuse solutions. In this paper we describe a case study to optimize E-Fuse long-term reliability. The methodology employed is for a Tungsten Silicide E-Fuse (WSi2), but the intention of this paper is to benchmark a qualification plan that can be employed for any E-Fuse, i.e. polysilicon, metal, or anti fuse qualification. The Prognostic Health Management (PHM) associated with an in die field programmable E-Fuse is investigated.E-Fuse can be used to develop autonomic microelectronic systems capable of in system repair, in system upgrade, in system customization, and in system failure prevention.

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“…A typical implementation is a poly (or Cu) fuse, where Joule heating is used to melt metal link and resulting resistance change is sensed by using a latch as shown in Fig. 1a [1][2][3][4][5][6][7][8][9][10][11]. Anti-fuse is one of the candidates for e-fuse [12][13][14].…”

Section: Introductionmentioning

confidence: 99%