A new compact model for monolithic transformers in silicon-based RFICs

Abstract

A new compact model for monolithic transformers on silicon substrates is presented. The new lumped-element equivalent circuit model employs transformer loops to represent skin and proximity effects including eddy current loss in the windings of the transformer. In addition to the self-resistances and self-inductances of the windings, the effects of the frequency-dependent mutual resistance and mutual inductance are included in the model. The new compact model has been applied to a stacked transformer on a 10-cm CMOS substrate. The extracted circuit model shows very good agreement with data obtained by full-wave electromagnetic simulation and measurement over the frequency range of 0.1-10 GHz.

A lumped element circuit model for monolithic transformers in silicon-based RFICs

“…The outer diameter of the transformer is 180 µm and the ports of each spiral are located on opposite sides of the transformer. Similar to [4], the four-port S-parameter data were obtained from the full-wave electromagnetic simulator HFSS [12] after calibration with available two-port measurement data.…”

“…The generalized transformer network topology adapted from [4], which takes into account the above discussed losses, is shown in Fig. 1.…”

“…For first-pass circuit design and reliable circuit simulations, accurate lumpedelement circuit models for on-chip transformers are important. To this end, various transformer topologies have been proposed and studied and several models along with their extraction procedures have been developed in recent years (e.g., [1][2][3][4]). …”

“…Reference [3] gives a review of the electrical performance of on-chip transformers and presents the characteristics of two-port and multi-port transformers. An equivalent circuit model incorporating frequency-dependent mutual resistance was introduced in [4]. The mutual resistance accounts for proximity effects in the windings; however, its implementation in terms of controlled sources does not automatically guarantee passivity of the model and can lead to convergence issues in some simulators.…”

Characterization, design and modeling of on-chip interleaved transformers in CMOS RFICs

“…Many research works have been done on the modeling of on-chip transformers with different shapes and layouts [4][5][6][7][8][9][10][11]. For example, Mohan et al [4] has presented two analytical transformer models for both tapped and stacked geometries.…”