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The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-m CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.

A T-coil network can be implemented as a high order filter for bandwidth extension. This technique is incorporated into the design of the input matching and output peaking networks of a low-noise amplifier. The intrinsic capacitances within the transistors are exploited as a part of the wideband structure to extend the bandwidth. Using the proposed topology, a wideband low-noise amplifier with a bandwidth of 3−8 GHz, a maximum gain of 16.4 dB and noise figure of 2.9 dB (min) is achieved. The total power consumption of the wideband lownoise amplifier from the 1.8 V power supply is 3.9 mW. The prototype is fabricated in 0.18 µm CMOS technology.

In this paper the power consumption and operating frequency of true single phase clock (TSPC) and extended true single phase clock (E-TSPC) frequency prescalers are investigated. Based on this study a new low power and improved speed TSPC 2/3 prescaler is proposed which is silicon verified. Compared with the existing TSPC architectures the proposed 2/3 prescaler is capable of operating up to 5 GHz and ideally, a 67% reduction of power consumption is achieved when compared under the same technology at supply voltage of 1.8 V. This extremely low power consumption is achieved by radically decreasing the sizes of transistors, reducing the number of switching stages and blocking the power supply to one of the D flip-flops (DFF) during Divide-by-2 operation. A divide-by-32/33 dual modulus prescaler implemented with this 2/3 prescaler using a Chartered 0.18 m CMOS technology is capable of operating up to 4.5 GHz with a power consumption of 1.4 mW.Index Terms-D-flip-flop (DFF), dual modulus prescalers, frequency dividers, frequency synthesizer, high speed digital circuits, true single-phase clock (TSPC).

A receiver front end designed in 0.18-m CMOS consisting of a low-noise amplifier and IQ mixers is presented. The front end's power consumption is controllable from 5.0 down to 1.4 mA. It is proposed to push the receiver requirements to the front end in order to efficiently control the overall power consumption based on the real-time required noise performance. We show that, under good channel conditions, this front end can save up to 70% of its nominal power consumption.