Design and Optimization of the Extended True Single-Phase Clock-Based Prescaler

Abstract

The power consumption and operating frequency of the extended true single-phase clock (E-TSPC)-based frequency divider is investigated. The short-circuit power and the switching power in the E-TSPC-based divider are calculated and simulated. A low-power divide-by-2/3 unit of a prescaler is proposed and implemented using a CMOS technology. Compared with the existing design, a 25% reduction of power consumption is achieved. A divide-by-8/9 dual-modulus prescaler implemented with this divide-by-2/3 unit using a 0.18-m CMOS process is capable of operating up to 4 GHz with a low-power consumption. The prescaler is implemented in low-power high-resolution frequency dividers for wireless local area network applications.

Design of Ultra Low Power 7.2 GHz True Single Phase Clock CMOS 2/3 Prescaler244 µW

“…All simulations are done by taking all parameters constant accept supply voltage. The supply voltageis 1.5 V for [14] and [15] prescalers and for other prescalers supply voltage is 1.8 V. From the simulation the [1] is most power efficient with 5.5 GHz operating frequency. While [2] can be operated up to 6.5 GHz which is highest for a TSPC based prescaler.…”

A low-power high-speed true single phase clock divide-by-2/3 prescaler

“…The power consumption versus the input frequency of the divide-by-2 circuit consisting of a single TSPC DFF, the proposed prescaler and the conventional prescaler based on [2,3,4] are simulated respectively as shown in Figs.3 a and b. The simulation results show that the conventional 2/3 prescaler can operate up to a maximum frequency of 4.5 GHz.…”

“…With the scaling down of CMOS processes, the speed improvement of the transistors makes it possible to replace the CML logic in less than 10-GHz band applications. Various TSPC prescaler are proposed to improve the speed of TSPC prescaler with less power penalty, mainly focusing on reducing the critical path delay [2], minimizing the logic gates [3] and reducing the number of transistors stacking [4]. But there is a tradeoff between the power consumption and the speed in the conventional ones.…”

Design of 77 GHz Radar Transmitter Using 13 GHz CMOS Frequency Synthesizer and Multiplier

“…TSPC 구조의 분주기는 디지털 회로로 CML 주파 수 분주기에 비해 동작 속도가 느리지만 간단한 회 로구조와 적은 전력 소모를 갖기 때문에 CML 분주 기 단의 출력인 3 GHz 대역의 주파수를 분주하기 위 하여 적합하다 [8] . 사용함으로써 분주단의 최종 출력은 위상 주파수 검 출기에서 기준 신호 50 MHz와 비교한다.…”