Characterization, design and modeling of on-chip interleaved transformers in CMOS RFICs

Abstract

This paper discusses the impacts of key geometrical parameters on the performance of interleaved transformers in CMOS radio frequency integrated circuits (RFICs). It also presents a compact circuit model for the transformer based on the ''2-p'' model of on-chip spiral inductors. All the RLC circuit elements can be calculated from the transformer's geometrical and process parameters. Verification with accurately calibrated electromagnetic (EM) simulation data demonstrates accurate performance prediction and good scalability for a wide range of transformers' layout.

Low-loss balun design and compact modeling for RF/millimeter-wave circuit application

“…As shown in Figure 1, the layout of the balun developed in this work is based on the well-known octagonal-shaped planar interleaved structure [4]. It is composed of two metal spirals without DC path.…”