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An ultra-low R on,sp 700 V DB-nLDMOS (dual P-buried-layer nLDMOS) which uses 0.35 μm technology and full ion implantation technology is proposed. Experimental results show that with 800 V BV ds , R on,sp is only 10.7 Ω • mm 2 which is the lowest value of triple RESURF (REduce SURface Field) LDMOS reported before. This mainly benefits from two aspects. First, thermal budgets of the process are strictly limited after implantation of the Pbury layer. Secondly, device sizes of the neck region are optimised to reduce R on,sp which also suppress the JFET effect of the triple RESURF LDMOS.

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A dual conduction paths segmented anode lateral insulated-gate bipolar transistor (DSA-LIGBT) which uses triple reduced surface field (RESURF) technology is proposed. Due to the hybrid structures of triple RESURF LDMOS (T-LDMOS) and traditional LIGBT, firstly, a wide p-type anode is beneficial to the small shift voltage .V ST ) and low specific on-resistance (R on;sp ) when the anode voltage (V A ) is larger than V ST . Secondly, a wide ntype anode and triple RESURF technology are used to get a low R on;sp when V A is less than V ST . Meanwhile, it can accelerate the extraction of electrons, which brings a low turn-off time (T off ). Experimental results show that: V ST is only 0.9 V, R on;sp (R on Area) are 11.7 and 3.6 mm 2 when anode voltage V A equals 0.9 and 3 V, respectively, the breakdown voltage reaches to 800 V and T off is only 450 ns.

An advanced low-cost and low-power high-voltage (HV) startup circuit which uses a 50 V pJFET and a 700 V T-nJFET (triple RESURF nJFET) is proposed. Compared with traditional technology, a mass of module area is saved. This mainly benefits from: first, with increase of V DS , I OFF (leakage current in off-state) can be quickly pinched off to a low value by pJFET without a large layout area which is needed for the traditional resistance method. Secondly, T-nJFET is located at the drain terminal of T-nLDMOS (triple RESURF LDMOS) with common drain electrode which also saves large area than traditional independent nJFET. Moreover, pJFET brings stable and low I OFF which leads to 4 mW P OFF (static power consumption in off-state) due to its low V P (pinch-off voltage) and high BV DS .Introduction: High-voltage (HV) JFET or depletion mode DMOS has been widely used in the HV startup circuit which is applied in highvoltage AC-DC converter, LED driver etc. [1][2][3][4][5]. Fig. 1a gives a traditional HV startup circuit [6]. Both independent HV nJFET and high resistance R1 need a large layout area which is not cost-effective. Therefore, dependent HV nJFET merged with double RESURF LDMOS is introduced to not only decrease the layout area, but it also needs high resistance R1 to turn off nJFET [7]. Moreover, low and stable I OFF is required to obtain low static power consumption for IC; however, it is quite difficult to obtain low static power consumption for the IC through the traditional method due to low-voltage coefficient of resistance and saturation characteristic of HV-nJFET.

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