A 0.35 &amp;#x03BC;m 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS

Mao, Kun; Qiao, Ming; Jiang, Lingli; Jiang, Huaping; Li, Zehong; Chen, Weizhong; Li, Zhaoji; Zhang, Bo

doi:10.1109/ispsd.2013.6694429

Cited by 8 publications

(2 citation statements)

References 5 publications

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“…Fig. 11 compares the BV ∼ R ON,SP relationship between this work and the prior art of LDMOS, which includes some experimental results [14], [36]- [38]. Although the conventional TLD+QVSJ studied in this work adopts the SJ technique, its performance is worse than the silicon limit, which reveals the impact of C trench .…”

Section: Figure 8 Comparison Of Potential Distribution In the Case Omentioning

confidence: 94%

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Cheng

Chen

et al. 2019

IEEE J. Electron Devices Soc.

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An improved trench lateral double-diffused MOSFET (T-LDMOS) is proposed. It has a quasi vertical super junction (QVSJ) drift region and adopts a resistive field plate (RFP) to help QVSJ satisfy charge-balance. The realization of RFP barely complicates the device fabrication, but it motivates QVSJ to significantly improve the relationship between breakdown voltage (BV) and specific on-state resistance (R ON,SP). The simulation results show that compared with the conventional QVSJ T-LDMOS, the proposed one gains the R ON,SP reduced by about 79% under the same BV requirement of about 500 V. It therefore presents an excellent figure of merit (FOM) (FOM = BV 2 /R ON,SP , Baliga's FOM) up to 29.8 MW/cm 2 , which is superior to the prior art and exhibits a bright prospect of saving energy. INDEX TERMS Trench LDMOS (T-LDMOS), quasi vertical super junction (QVSJ), resistive field plate (RFP).

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Section: Figure 8 Comparison Of Potential Distribution In the Case Omentioning

confidence: 94%

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

Cheng

Chen

et al. 2019

IEEE J. Electron Devices Soc.

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“…In order to ameliorate curvature effect of the source centered architecture, dumbbell-shaped structure with enlarged radius at the source region is adopted in [8], and fan-shaped source with slightly doped n-type well and multiple buried p-type field shaping layers in the source fingertip region for a 700-V LDMOS is presented in [9]. The high-voltage LDMOS with BV of above 700 V is one of the most demanding technologies for switched-mode power supply [9][10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

A novel substrate termination technology for lateral double-diffused MOSFET based on curved junction extension

Qiao¹,

Wu²,

Zhang³

et al. 2014

Semicond. Sci. Technol.

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In this paper, a novel substrate termination technology (STT) for lateral double-diffused MOSFET (LDMOS) based on curved junction extension is proposed and experimentally demonstrated. A low-doped P-substrate, which is inserted in the curved region of the LDMOS, adjusts the high-doped abrupt P-body/N-drift junction with small curvature radius to low-doped P-sub/N-drift junction with large curvature radius, thus reducing peak electric field and avoiding premature avalanche breakdown at the curved abrupt P-body/N-drift junction. The proposed STT has been applied to a super junction (SJ) LDMOS. The experimental results show that the SJ LDMOS with the proposed STT exhibits off-state breakdown voltage (BV) of 800 V, which is the highest BV for the reported SJ LDMOS by far.

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Study of Ultra High Voltage 500V NLDMOS with Aggressive Design of Drift Region

Duan

Yuan

et al. 2019

2019 China Semiconductor Technology International Conference (CSTIC)

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A 0.35 μm 700 V BCD technology with self-isolated and non-isolated ultra-low specific on-resistance DB-nLDMOS

Cited by 8 publications

References 5 publications

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

A Trench LDMOS Improved by Quasi Vertical Super Junction and Resistive Field Plate

A novel substrate termination technology for lateral double-diffused MOSFET based on curved junction extension

Study of Ultra High Voltage 500V NLDMOS with Aggressive Design of Drift Region

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