700 V ultra‐low on‐resistance DB‐nLDMOS with optimised thermal budget and neck region

Mao, Kun; Qiao, Ming; Li, Zhaoji; Zhang, Bo

doi:10.1049/el.2013.2287

Cited by 7 publications

(4 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The specific on-resistance increases with the L 1 , L P and T P as shown in Eq. (2). Actually, the deep T P and long L P means a narrow current flow channel under the P + region, leading to a large R ld2.…”

Section: On Resistancementioning

confidence: 99%

“…One of the main issues when designing power LDMOS is the trade-off between the breakdown voltage (BV) and specific on-resistance (R sp ) [2]. The REduce SURface Field (RESURF) technique is the most widely used method for designing lateral high voltage and low onresistance MOS devices [3,4], but Single RESURF (S-RESURF) technique must ensure a low drift region concentration to make the epitaxial layer deplete completely, otherwise the high drift concentration will lead to the P well N drift junction electric field premature reaching the critical electric field of silicon, thus reducing the breakdown voltage [5,6].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Low Specific On-resistance SOI LDMOS Device with P⁺P-top Layer in the Drift Region

Yao¹,

Guo²,

Xu³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-In this paper, a novel low specific onresistance SOI LDMOS Device with P+P-top layer in the drift region is proposed and investigated using a two dimensional device simulator, MEDICI. The structure is characterized by a heavily-doped P + region which is connected to the P-top layer in the drift region. The P + region can modulates the surface electric field profile, increases the drift doping concentration and reduces the sensitivity of the breakdown voltage on the geometry parameters. Compared to the conventional D-RESURF device, a 25.8% decrease in specific on-resistance and a 48.2% increase in figure of merit can be obtained in the novel device. Furthermore, the novel P + P-top device also present cost efficiency due to the fact that the P + region can be fabricated together with the P-type body contact region without any additional mask.

show abstract

Section: On Resistancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low Specific On-resistance SOI LDMOS Device with P⁺P-top Layer in the Drift Region

Yao¹,

Guo²,

Xu³

et al. 2014

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…Unfortunately, the field peak induced at the end of the MFP easily causes premature breakdown and a high intrinsic leakage current is brought by the RFP in the ON-state. The REduced SURface Field (RESURF) technology not only increases the BV, but also improves the R ON,sp through charge compensation between the N-drift region and P-substrate/P-top layer/P-buried layer (i.e., single/double/triple RESURF) [5]- [13]. However, the P-top or P-buried layer occupies a part of the current path in the N-drift in the ON-state [5]; moreover, there is a Junction Field Effect Transistor region between the P-top or P-buried layer and the N-drift region.…”

Section: Introductionmentioning

confidence: 99%

Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage

Luo

Wei

Shi

et al. 2014

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

A novel Lateral Double-diffusion Metal Oxide Semiconductor (LDMOS) is proposed to enhance its breakdown voltage (BV) and reduce specific ON-resistance (R ON,sp ), and its mechanism is investigated by simulation. It features a junction field plate (JFP) at surface and an N+ floating layer (NFL) in the P-substrate. The lateral variation doping JFP not only modulates the surface electric field (E-field) distribution to improve the BV, but also allows a high N-drift doping concentration and thus reduces the R ON,sp owing to the charge compensation effect between the N-drift region and P region in the JFP in the OFF-state. The heavily doped NFL is not fully depleted and thus is an equipotential layer in the lateral direction. It thus reshapes the equipotential contours at both the source and drain sides, avoiding the E-field concentration and premature breakdown under the drain; moreover, the additional vertical diode is induced between the NFL and P-sub and it thus extends the depletion width in P-sub, both of which increase the BV. The R ON,sp and BV of the JFP-NFL LDMOS is improved by 47% and 63%, respectively, compared with those of a conventional LDMOS at the same dimension. The JFP-NFL LDMOS achieves a superior tradeoff between R ON,sp and BV to the different single-, double-, and triple-REduced SURface Field LDMOSFETs with planar technology.Index Terms-Breakdown voltage (BV), high voltage, junction field plate (JFP), N+ floating layer (NFL), specific ON-resistance.

show abstract

“…The BV ds is up to 780 Y with only 10A-Q·mm 2 Ron . s p which benefits from triple RESURF technology and optimal neck region [5].…”

Section: Introductionmentioning

confidence: 99%

A 700 V low specific on-resistance self-isolated DB-nLDMOS

Mao

Qiao

Zhang

et al. 2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

View full text Add to dashboard Cite

a 700 V self-ISO (isolated) DB-nLDMOS (dual P buried-layer nLDMOS) without epitaxy is proposed in this paper. By separately implanting deep junction NWELLs, drift region of low doping concentration in neck region is achieved.This alleviates the concentration of the electric field and avoids premature avalanche breakdown around the bird's beak.Furthermore, introduction of triple RESURF (reduce surface field) technology and optimal device sizes benefit for ultra-low Ron,s p (specific on-resistance). Finally, this ISO DB-nLDMOS is experimentally integrated in a 700 V BCD process platform.Testing results show that proposed device achieves 780-V BVd" 1 0.4-Q·mm 2 Ron,s p and 20-V floating voltage of source electrode.

show abstract

700 V ultra‐low on‐resistance DB‐nLDMOS with optimised thermal budget and neck region

Cited by 7 publications

References 5 publications

Low Specific On-resistance SOI LDMOS Device with P⁺P-top Layer in the Drift Region

Low Specific On-resistance SOI LDMOS Device with P⁺P-top Layer in the Drift Region

Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage

A 700 V low specific on-resistance self-isolated DB-nLDMOS

Contact Info

Product

Resources

About

700 V ultra‐low on‐resistance DB‐nLDMOS with optimised thermal budget and neck region

Cited by 7 publications

References 5 publications

Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

Novel Reduced ON-Resistance LDMOS With an Enhanced Breakdown Voltage

A 700 V low specific on-resistance self-isolated DB-nLDMOS

Contact Info

Product

Resources

About

Low Specific On-resistance SOI LDMOS Device with P⁺P-top Layer in the Drift Region

Low Specific On-resistance SOI LDMOS Device with P⁺P-top Layer in the Drift Region