Effect of p-Type Buried Layer Dose on Hot Carrier Degradation of R_ONin 700 V Triple RESURF nLDMOS

Theoretical study on optimization criterion of the triple RESURF lateral power devices via virtual junction concept

“…In the wake of the single reduced surface field (S-RESURF) technique, enormous efforts have been directed toward the improvement of the BV-R on trade-off. [1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17] Among them, the double RESURF (D-RESURF) and triple RESURF (T-RESURF) techniques have emerged as excellent approaches to improve BV-R on trade-off via creating additional conduction paths. 16,[18][19][20][21] The most distinctive feature of a T-RESURF device is the P-buried layer among the drift region.…”

Channel Length Optimization for Planar LDMOS Field-Effect Transistors for Low-Voltage Power Applications

“…However, complex device structures are often introduced in these proposed technologies which make the industrial fabrication process very difficult and costly. Furthermore, even though device miniaturization is crucial for all voltage ranges, in the past few decades, most studies have been done on large LDMOS devices for mid-voltage and high-voltage applications [15][16][17][18][19][20][21][22][23][24][25][26][27]. And unfortunately, a thorough study on scaling of the planar LDMOS technology, limited to a straightforward planar device design, has not yet been performed.…”