Abstract:We identify an optimum channel length for planar Laterally Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors, in terms of the specific on-resistance, through systematic device simulation and optimization. We simulate LDMOS devices with different channel lengths ranging from 100 nm to 10 nm, modifying the length of the drift region and doping concentration of the body region to match a predetermined leakage current suitable for lowvoltage power applications (3.3V and 5V). For devices with a ch… Show more
“…Thus, it is shown that the variations in conduction characteristics are caused mainly by the number of GB located in the channel 3 . The V th is defined by the constant-current method, which determines the V th as the V g value for I d = 10 − 7 A/µm 15 . Figure 3 Electron potential energy of the proposed devices with and without GB at a read operation.…”
In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.
“…Thus, it is shown that the variations in conduction characteristics are caused mainly by the number of GB located in the channel 3 . The V th is defined by the constant-current method, which determines the V th as the V g value for I d = 10 − 7 A/µm 15 . Figure 3 Electron potential energy of the proposed devices with and without GB at a read operation.…”
In this paper, a capacitorless one-transistor dynamic random access memory (1 T-DRAM) based on a polycrystalline silicon (poly-Si) metal-oxide-semiconductor field-effect transistor with the asymmetric dual-gate (ADG) structure is designed and analyzed through a technology computer-aided design (TCAD) simulation. A poly-Si thin film was used within the device due to its low fabrication cost and feasibility in high-density three-dimensional (3-D) memory arrays. We studied the transfer characteristics and memory performances of the single-layer ADG 1 T-DRAMs and the 3-D stacked ADG 1 T-DRAMs and analyze the reliability depending on the location and the number of grain-boundaries (GBs). The relative standard deviation (RSD) of the threshold voltages (Vth) is depending on the location and the number of GBs. The RSDs of the single-layer ADG 1 T-DRAM and the 3-D stacked ADG 1 T-DRAM are 1.58% and 0.68%, respectively. The RSDs of retention time representing the memory performances are 54.7% and 41%, respectively. As a result of the 3-D stacked structure, the averaging effect occurs, which greatly aids in improving the reliability of the memory performances as well as the transfer characteristics of 1 T-DRAMs depending on the influence of GBs. The proposed 3-D stacked ADG 1 T-DRAM helps implement a high-reliability single-cell memory device.
“…The V th values were extracted using the constant-current method at 100 nA μm −1 . [27][28][29] Figure 3 presents the transfer curves of the 200 JL bulk-FinFET-based 1T-DRAM samples fabricated using the TiN, MoN, TaN and WN gate materials. Note that each metal material consists of two or more grains and each grain has a different WF value depending on the grain orientation.…”
Section: Device Structure and Simulation Methodsmentioning
confidence: 99%
“…For the TaN metal gate, all the V th values could not be extracted because all drain currents in the I ds -V gs curves were greater than 100 nA μm −1 , which was a reference value. [27][28][29] The standard deviations (SDs) for the V th values were 14.8 mV, 46.0 mV and 46.0 mV, respectively. The relative standard deviations (RSDs) were 5.43%, 8.83% and 12.6%, respectively.…”
Section: Device Structure and Simulation Methodsmentioning
In this study, we developed a capacitorless dynamic random-access memory (DRAM) (1T-DRAM) device based on a junctionless (JL) bulk-fin field-effect transistor structure with excellent reliability and negligible variability against work-function variation (WFV). We investigated the variation in the transfer characteristics and memory performance of the memory cell owing to WFV. In particular, to investigate the WFV effect, we analyzed the transfer characteristics and memory performance of 200 samples using four metal-gate materials—TiN, MoN, TaN, and WN. Consequently, we discovered that the WFV affected the transfer characteristics of the gate-all-around JL-field-effect transistor. However, the proposed 1T-DRAM demonstrated that the sensing margin and retention time produced minimal effect owing to the adoption of a structure storing holes in the fin region. Consequently, the proposed 1T-DRAM exhibited strong WFV immunity and excellent reliability for memory applications.
“…Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) field-effect transistors are commonly used in lowvoltage [1], [2], mid-voltage [3], [4], and high-voltage [5]- [8] applications because of their promising performance and their use of silicon technology. Ever growing commercial applications of LDMOS transistors has attracted much attention in the research community [9]- [11].…”
We analytically and numerically investigate the performance of Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistors with Semi-circular Field OXide (S-FOX) focusing on midvoltage (30 V -100 V) power applications. We derive an analytical relation between breakdown voltage and on-resistance to realize the ideal behavior of the drift region for an LDMOS with S-FOX. Then, we find the optimized drift doping concentration minimizing the on-resistance at a given breakdown voltage. We introduce a new figure-of-merit for the drift region of a lateral device with S-FOX. We finally verify our ideal analytical findings with numerical results modeled and simulated in a commercial Technology Computer-Aided Design (TCAD).
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