LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and Verification

Saadat, Ali; Put, Maarten L. Van de; Edwards, Hal; Vandenberghe, William G.

doi:10.1109/jeds.2022.3169702

Cited by 4 publications

(4 citation statements)

References 43 publications

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“…Ref. [26] Baliga's curve seems high than that of Ref. [25], but the author didn't give out explanations.…”

Section: Bfom Resultsmentioning

confidence: 90%

“…[25] and Ref. [26] This article has been accepted for publication in IEEE Journal of the Electron Devices Society. This is the author's version which has not been fully edited and content may change prior to final publication.…”

Section: Bfom Resultsmentioning

confidence: 99%

“…Different with the Ref. [26], D is still considered as uniform and can be expressed as > JEDS-2023-08-0209-R = where is defined as a modulator factor. It is determined by the current length and the current width , and a larger depletion region (proportional to ) or a higher value will yield a better (higher) factor .…”

Section: − Fom Characters Fom(figures-of-merits) Character Relating T...mentioning

confidence: 99%

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Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low , (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length L, field plate thickness H, and slot contact width W, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that , can achieve as low as 6.9m•mm 2 when the source-drain (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W=10 m) and very large devices (W= 2mm). Index Terms-Contact field plate (CFP), Figures of merits (FOM), Lateral double diffusion metal oxide semiconductor (LDMOS), Specific on-resistance ( , )

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“…Ref. [26] Baliga's curve seems high than that of Ref. [25], but the author didn't give out explanations.…”

Section: Bfom Resultsmentioning

confidence: 90%

Section: Bfom Resultsmentioning

confidence: 99%

Section: − Fom Characters Fom(figures-of-merits) Character Relating T...mentioning

confidence: 99%

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Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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“…Manually determining the optimal FOX is a painstaking process. A traditional method to understand the behavior of LDMOS with field oxide structure is to find the analytical solution [17], [18]. There is some research combine TCAD simulation and machine learning to accelerate the development of simulation works in different areas [19], [20], [21], [22], [23], [24], [25], but to date, no automated methodology is available to determine the optimal doping profile for a given FOX shape.…”

Section: Introductionmentioning

confidence: 99%

Algorithmic Optimization of Transistors Applied to Silicon LDMOS

Chuang,

Saadat,

Van De Put

et al. 2023

IEEE Access

Self Cite

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We propose a pioneering approach that integrates optimization algorithms and technology computer-aided design to automatically optimize laterally-diffused metal-oxide-semiconductors (LDMOS) with a field-oxide structure. We define the ratio of the square of the breakdown voltage divided by the specific on-resistance as the figure-of-merit (FOM) and the objective function of our optimization. We compare the performance of three different algorithms: Nelder-Mead, Powell, and Bayesian Optimization. We show how the LDMOS performance evolves as each of the three optimization algorithms reach their optimized structure. We show that a straightforward Nelder-Mead optimization leads to a local optimum when optimizing over six input parameters. We find that Bayesian Optimization is the most data-efficient method to find the global optimized structure in the multi-domain design space.INDEX TERMS Bayesian optimization, LDMOS, nelder-mead algorithm, power semiconductor device, powell algorithm, step gate field oxide structure.

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Influence of Structure Parameters on the RoN, sp of Quasi- Vertical Power DMOS Compatible with 0.18μm BCD Process

Wu,

Wei,

Wang

et al. 2024

2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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LDMOS Drift Region With Field Oxides: Figure-of-Merit Derivation and Verification

Cited by 4 publications

References 43 publications

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Algorithmic Optimization of Transistors Applied to Silicon LDMOS

Influence of Structure Parameters on the RoN, sp of Quasi- Vertical Power DMOS Compatible with 0.18μm BCD Process

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