No abstract

No abstract

M-of-N threshold gates with hysteresis form a class of circuit elements that have important application in NULL Convention Logic ", a novel asynchronous logic design methodology. General design guidelines for these M-of-N gates are presented using CMOS technology. Three types of circuit implementations are discussed: static, semi-static and dynamic. In addition, initialization techniques are presented for use in establishing a known initial state.

No abstract

No abstract

Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the verification task might be significantly reduced. This method is implemented using Satisfiability (SAT)-solvers and is successfully tested on realistic design examples having tens of thousands of gates.

This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-level) pipelining of Manchester adders with two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement of performance.

No abstract