CMOS circuit design of threshold gates with hysteresis

Sobelman, Gerald E.; Fant, Karl M.

doi:10.1109/iscas.1998.706841

Cited by 92 publications

(57 citation statements)

References 3 publications

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“…3 (d). The principle of transistor-level threshold gate design can be found in [7]. The design of computational blocks, registers and completion detection blocks using threshold gates is available in [8].…”

Section: Null Convention Logicmentioning

confidence: 99%

Soft error in FPGA-implemented asynchronous circuits

Kuang¹,

Bai²

2011

2011 VII Southern Conference on Programmable Logic (SPL)

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In this paper, we investigate the mechanism of soft error generation and propagation in asynchronous circuits which are implemented on FPGAs. The effects of the soft errors on Quasi-delay-insensitive (QDI) asynchronous circuits are analyzed. The results show that �� easier to detect the soft error in asynchronous circuits implemented on FPGAs so that FPGAs can be reprogrammed, compared with traditional synchronous circuits.

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Section: Null Convention Logicmentioning

confidence: 99%

Soft error in FPGA-implemented asynchronous circuits

Kuang¹,

Bai²

2011

2011 VII Southern Conference on Programmable Logic (SPL)

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“…Linear programming and tabulation methods have been used in [3] to determine if a function is threshold or not. A CMOS implementation of threshold gates can be found in [9]. A survey of VLSI implementations of threshold logic can be found in [10].…”

Section: E Previous Workmentioning

confidence: 99%

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies

Zhang

Gupta

Lin

et al. 2008

Design, Automation, and Test in Europe

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Abstract-We propose an algorithm for efficient threshold network synthesis of arbitrary multi-output Boolean functions. The main purpose of this work is to bridge the wide gap that currently exists between research on the development of nanoscale devices and research on the development of synthesis methodologies to generate optimized networks utilizing these devices. Many nanotechnologies, such as resonant tunneling diodes (RTD) and quantum cellular automata (QCA), are capable of implementing threshold logic. While functionally correct threshold gates have been successfully demonstrated, there exists no methodology or design automation tool for general multi-level threshold network synthesis. We have built the first such tool, ThrEshold Logic Synthesizer (TELS), on top of an existing Boolean logic synthesis tool. Experiments with about 60 multi-output benchmarks were performed, though the results of only 10 of them are reported in this paper because of space restrictions. They indicate that up to 77% reduction in gate count is possible when utilizing threshold logic, with an average reduction being 52%, compared to traditional logic synthesis. Furthermore, the synthesized networks are well-balanced, and hence delay-optimized.

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“…An NCL threshold gate with hysteresis [17] is a gate whose set and reset functions are not combinational, but rather are sequential. Once the gate is set, the output does not change until the reset condition occurs, and once it is reset, the output does not change until the set condition occurs.…”

Section: Ncl Threshold Gates With Hysteresis a 2ncl Circuit Ismentioning

confidence: 99%

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Jeong

Nowick

2007

2007 Asia and South Pacific Design Automation Conference

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Abstract-As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

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CMOS circuit design of threshold gates with hysteresis

Cited by 92 publications

References 3 publications

Soft error in FPGA-implemented asynchronous circuits

Soft error in FPGA-implemented asynchronous circuits

Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

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