An asynchronous 2-D discrete cosine transform chip

Smith, Ronan J.; Fant, Karl M.; Parker, David; Stephani, R.; Wang, Ching‐Yi

doi:10.1109/async.1998.666508

Cited by 6 publications

(3 citation statements)

References 27 publications

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“…Design flows like Tangram developed by Philips Research [2,11], Balsa developed at the University of Manchester [1] and the one used at Theseus Logic [13] have proved to be effective in designing academic and industrial asynchronous circuits [8,16,14]. Nevertheless, the proprietary or non-standard nature of these design flows has been a major obstacle to their widespread adoption.…”

Section: Introductionmentioning

confidence: 99%

Automating the design of an asynchronous DLX microprocessor

Amde

Blunno

Sotiriou

2003

Proceedings of the 40th Annual Design Automation Conference

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In this paper the automated design of an asynchronous DLX microprocessor is presented. The microprocessor has been designed beginning with a standard RTL-like Verilog specification and the Pipefitter design flow has been used to automatically generate both the specification for the direct implementation of the Control Unit and a synthesisable Verilog specification of the Data Path. The architecture of the DLX is locally synchronous and globally asynchronous and the delay elements for the generation of the local clock signal are automatically produced by Pipefitter as well.The following steps of the design flows (i.e., logic synthesis, technology mapping, placement and routing) have been completed using standard tools leading to the final layout of the circuit.The final microprocessor implements all the functionality of a standard DLX (with the exception of the floating point unit) and supports its whole set of instructions.Some considerations on the area occupation of the microcontroller will be presented in the last section of this paper.

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Section: Introductionmentioning

confidence: 99%

Automating the design of an asynchronous DLX microprocessor

Amde

Blunno

Sotiriou

2003

Proceedings of the 40th Annual Design Automation Conference

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“…This means that outputs of the one-bit adder must provide information about completion of inputs and internal gates. One such implementation is a 4 gate Null Convention Logic full adder from [32]. A common property of delay-insensitive adders under 4-phase handshake discipline is sequential (state holding) behavior of the gates.…”

Section: Two-dimensional Pipeliningmentioning

confidence: 99%

“…Also for simplicity we built 4x4 versions of the multipliers. We start from a simple pipelined structure based on ripple carry adder [32] with broadcasting of A, B and the completion tree to produce the acknowledge (M1). We add pipelining of the multiplicand (A) -"half-mesh" (M2).…”

Section: Multipliers With Different Organizationsmentioning

confidence: 99%

Design of delay-insensitive three dimension pipeline array multiplier for image processing

Taubin

Fant²,

McCardle

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

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This paper presents a novel delay-insensitive three dimension pipeline array multiplier. The organization combines deep (gate-level) pipelining of Manchester adders with two dimensional cross-pipeline mesh for multiplicand and multiplier propagation and partial product bits calculation. Fine grain pipelining with elimination of broadcasting and completion trees leads to high-throughput without use of dynamic logic that leaves the door open for further improvement of performance.

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