Various kinds of asynchronous interconnect and synchronisation mechanisms are being proposed for designing low power, low emission and high-speed SOCs. They facilitate modular design and possess greater resilience to fabrication time inter-chip and run-time intra-chip process variability. They can provide a solution for low power consumption in chips and simplify global timing assumptions, e.g. on clock skew, by having asynchronous communication between modules. A few methodologies, including globally asynchronous, locally synchronous and desynchronisation, aim at leveraging the benefits of both synchronous and asynchronous design paradigms. The authors survey various methodologies used for leveraging asynchronous on-chip communication. They investigate various GALS based implementations, desynchronisation strategies and asynchronous network-on-chip (NoC) designs.
Abstract-We consider the problem of code acquisition at low signal to interference and noise ratio (SINR) in packetbased spread spectrum communications, where a centralized "pilot" synchronization signal and high-precision oscillators are not available. Such problems arise in the context of ad-hoc networks, for example, which require fast code acquisition times and gradual degradation of the network with decreasing SINR.We motivate the use of the "postdetection integration" approach, which utilizes the energy of multiple bits in a packet, for code acquisition at low SINR. We present the implementation of a fully parallel architecture which simultaneously looks at all possible code alignments over multiple bits. This leads to a drastic reduction in acquisition time compared to serial search based methods. We report some preliminary simulation and experimental results from a hardware prototype of a transceiver on which the code acquisition algorithm was implemented.
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