Automating the design of an asynchronous DLX microprocessor

Abstract

In this paper the automated design of an asynchronous DLX microprocessor is presented. The microprocessor has been designed beginning with a standard RTL-like Verilog specification and the Pipefitter design flow has been used to automatically generate both the specification for the direct implementation of the Control Unit and a synthesisable Verilog specification of the Data Path. The architecture of the DLX is locally synchronous and globally asynchronous and the delay elements for the generation of the local clock signal are automatically produced by Pipefitter as well.The following steps of the design flows (i.e., logic synthesis, technology mapping, placement and routing) have been completed using standard tools leading to the final layout of the circuit.The final microprocessor implements all the functionality of a standard DLX (with the exception of the floating point unit) and supports its whole set of instructions.Some considerations on the area occupation of the microcontroller will be presented in the last section of this paper.

Utilizing timing error detection and recovery to dynamically improve superscalar processor performance

“…However, in recent years promising developments have been made as asynchronous designs have begun to gain acknowledgment. Amde et al (2003) presents a tool automated design of an asynchronous DLX processor. It seems that, although still in their early stages of acceptance, asynchronous designs offer a promising alternative to the worst case limits that plague traditional synchronous designs.…”