This paper presents how the current-sensing completion detection (CSCD) method can be applied for standard cell based digital system design. With theproposedmethod, conventional synchronous CMOS logic circuit blocks can easily be modified for self-timed asynchronous operation. To illustrate the usage of the method a self-timed CSCD multiplier-accumulator (MAC) was constructed. The simulation results and the VHDL synthesized layouts of the CSCD MAC show that the CSCD method and the various proposed design practices are well usable for the construction of selftimed asynchronous logic systems.
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