Design of delay-insensitive three dimension pipeline array multiplier for image processing

Taubin, Alexander; Fant, Karl M.; McCardle, J.

doi:10.1109/iccd.2002.1106755

Cited by 7 publications

(4 citation statements)

References 28 publications

(38 reference statements)

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“…More developed error detection techniques, such as robust protection, need to be used. Other weaknesses of "classical" self-timed implementations [23] discovered in [18] could be effectively dealt with by asynchronous fine-grain multidimensional pipelined structures [24]. We are now starting development of robust asynchronous fine-grain pipelined implementations of AES using EDA tools under development in Boston University.…”

Section: Advantages Of Proposed Robust Architecture and Future Tasksmentioning

confidence: 98%

Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard

Karpovsky

Kulikowski

Taubin

2004

International Conference on Dependable Systems and Networks, 2004

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113

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We present a method of protecting a hardware implementation of the Advanced Encryption Standard (AES) against a side-channel attack known as Differential Fault Analysis attack. The method uses systematic nonlinear (cubic) robust error detecting codes. Errordetecting capabilities of these codes depend not just on error patterns (as in the case of linear codes) but also on data at the output of the device which is protected by the code and this data is unknown to the attacker since it depends on the secret key. In addition to this, the proposed nonlinear (n,k)-codes reduce the fraction of undetectable errors from 2 r to 2 2 r as compared to the corresponding (n,k) linear code (where n-k=r and k>=r). We also present results on a FPGA implementation of the proposed protection scheme for AES as well as simulation results on efficiency of the robust codes.

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Section: Advantages Of Proposed Robust Architecture and Future Tasksmentioning

confidence: 98%

Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard

Karpovsky

Kulikowski

Taubin

2004

International Conference on Dependable Systems and Networks, 2004

Self Cite

113

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“…When connected in Ripple Carry Adder fashion, propagating carry signal along consecutive adder cells in the same row (Figure 1), completion time and throughput of DISCA could benefit significantly from this early carry generation feature. However NCL style DISCA implementations in literature either do not employ bit-level pipelining [8,9] or are pipelined in the multiplier array style [10], so that each adder unit operates independently from other adders in the same row and delivers its sum and carry outputs to the next row of adders in the array. In this study, the NCL style DISCA of [10] pipelined in three dimensions for multiplier array is modified to apply bit-level pipelining in two dimensions: In the directions of carry and sum flow, with dedicated ACK/REQ signals controlling each dimension ( Figure 2).…”

Section: A Delay Insensitive Carry Save Addermentioning

confidence: 99%

“…However NCL style DISCA implementations in literature either do not employ bit-level pipelining [8,9] or are pipelined in the multiplier array style [10], so that each adder unit operates independently from other adders in the same row and delivers its sum and carry outputs to the next row of adders in the array. In this study, the NCL style DISCA of [10] pipelined in three dimensions for multiplier array is modified to apply bit-level pipelining in two dimensions: In the directions of carry and sum flow, with dedicated ACK/REQ signals controlling each dimension ( Figure 2). Simulations of the pipelined DICSA indicate an interaction of DATA and NULL waves for some input sets, hence a violation of Delay Insensitivity.…”

Section: A Delay Insensitive Carry Save Addermentioning

confidence: 99%

Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders

Ismailoglu

Askar

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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In this study, two asynchronous delay insensitive adder topologies in Null Convention Logic [1] style are adopted for bit-level pipelining: The reduced Null Convention Logic Adder [2] and a Null Convention Carry Save Adder. When pipelined at bit-level, early carry generation feature of both adders violate the requirements of delay insensitivity. To solve this problem, new topologies are proposed. Resultant adders maintain both reliable delay insensitive operation and speedup advantages of early carry generation, with O(log n) average completion time for n-bit addition and -as a result of bit-level pipelining-constant throughput against increased bit-length.

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“…-Asynchronous multi-dimensional (e.g. 3D) pipelined array architectures [11] can eliminate data dependent timing and thereby secure implementations against DEMA and differential timing analysis (DTA).…”

Section: Asynchronous Circuit Designmentioning

confidence: 99%

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Kulikowski

Smirnov

Taubin

2006

Lecture Notes in Computer Science

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Abstract. Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite their benefits for security applications they have not been adapted to current mainstream designs due to the lack of electronic design automation support and their nonstandard or proprietary design methodologies. We present a novel asynchronous fine-grain pipeline synthesis methodology that addresses these limitations. It allows synthesis of asynchronous quasi delay insensitive circuits from standard high-level hardware description language (HDL) specifications. We briefly present a proof of concept differential dynamic power balanced micropipeline library cells that are approximately 6 times more balanced than the best (differential dynamic) cells designed using previous balancing methods. An implementation of the Advanced Encryption Standard based on these balanced cells and synthesized using our tool flow shows a 6.6 times throughput improvement over the synchronous automatically pipelined implementation using the same TSMC 0.18μm technology synthesized from the same HDL specification.

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Design of delay-insensitive three dimension pipeline array multiplier for image processing

Cited by 7 publications

References 28 publications

Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard

Robust protection against fault-injection attacks on smart cards implementing the advanced encryption standard

Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

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