Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Abstract

Abstract. Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite their benefits for security applications they have not been adapted to current mainstream designs due to the lack of electronic design automation support and their nonstandard or proprietary design methodologies. We present a novel asynchronous fine-grain pipeline synthesis methodology that addresses these limitations. It allows synthesis of asynchronous quasi delay insensitive circuits from standard high-level hardware description language (HDL) specifications. We briefly present a proof of concept differential dynamic power balanced micropipeline library cells that are approximately 6 times more balanced than the best (differential dynamic) cells designed using previous balancing methods. An implementation of the Advanced Encryption Standard based on these balanced cells and synthesized using our tool flow shows a 6.6 times throughput improvement over the synchronous automatically pipelined implementation using the same TSMC 0.18μm technology synthesized from the same HDL specification.

Elastic Circuits

“…An extreme case of asynchronous elastic pipelining-gatelevel pipelining, can combine high throughput with low voltage, given the robustness achieved by the insensitivity to variability provided by gate-level completion detection. Furthermore, this approach is suitable for applications related to hardware security [112], since the combination of asynchronous elasticity and balanced dynamic gates is essential for the design of devices that are highly resistant to side-channel attacks (dualrail dynamic gates are easier to balance, completion detection makes early propagation attack problematic, glitch attacks are not possible, etc., see [63], [64] for details).…”

Mitigating information leakage during critical communication using S*FSM

“…Equations (14) and (15), formally define N peak with unique and identical technology dependent weighting factors w 1 , w 2 , respectively. While previous works were also concerned with switching activity [36] (16), our current discussion relaxes this constraint in favour of our core security objectives. The minimisation of N peak is accomplished by forcing additional restrictions on HD/HDR -mainly minimising c 2 in (13), respectively,…”

Delay Insensitive Ternary CMOS Logic for Secure Hardware

“…Techniques based on balancing power fluctuation include new CMOS logic gates [31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46], which go through a full charge/discharge cycle for each data processed. Asynchronous circuits, especially dual-rail encoded logic, have been well studied for anti-DPA because of the fixed switching activities during each DATA-Spacer cycle [47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65]. Other power balancing methods include modifying the algorithm execution [66][67][68][69], compensating current at the power supply node [70][71][72][73], and using subthreshold operation [74].…”