Elastic Circuits

Carmona, Josep; Cortadella, Jordi; Kishinevsky, Michael; Taubin, Alexander

doi:10.1109/tcad.2009.2030436

Cited by 81 publications

(54 citation statements)

References 109 publications

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“…Notice that a switch sends different stall signals to its upstream switches, in fact, only the upstream switch that grants the buffer could have its stall signal active. This communication scheme is called elasticity [22]. Figure 7 shows the communication flow control between the NI injector/ejector and the subnetwork is attached.…”

Section: Network Implementationmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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Section: Network Implementationmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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“…The idea was introduced by Carloni et al [12] at system level and was formalised by Carmona et al [9] for exploitation in CAD flows, which made it applicable from transistors to the system level. Elasticity comes with costs: if the designer chooses to apply elasticity at a fine-grained level, its communication costs may prohibitively dominate computation costs.…”

Section: A Elasticitymentioning

confidence: 99%

“…Here we target eTeak [8] which is an extension to Teak. It incorporates synchronous elasticity [9] as a common timing discipline to achieve a deterministic (cycle-accurate) behaviour.…”

Section: Introductionmentioning

confidence: 99%

De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits

Mamaghani

Garside

Edwards

2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

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Abstract-Asynchronous VLSI programming provides a flexible abstract formalism for concurrent systems but the is an issue for industrial adoption. The asynchronous design paradigm provides 'elasticity' enabling the system to tolerate delays in communication and computation but can impose a prohibitive communication overhead when applied at a fine-grained level. This paper proposes 'De-elastisation' in a CAD flow for asynchronous dataflow networks to improve the circuits' performance and area. To preserve the architectural advantages of asynchronous design (e.g. short cycles), circuits are classified into blocking and non-blocking loops which the De-elastisation scheme relies upon. The technique is incorporated in the Teak CAD flow. Experimental results on substantial case studies show significant performance and area improvements. This work shows 3× improvement for the first category of circuits, suitable for iterative realisations and DSP-like architectures and 4× for the second category which are suitable for concurrent realisations.

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“…vout [1] rin [1] vout [2] rin [2] vout [3] rin [3] data_out arbiter vin [1] rout [1] vin [2] rout [2] vin [3] rout [3] data_in EB EB EB Fig. 4.…”

Section: Multithreaded Elastic Protocol and Buffersmentioning

confidence: 99%

“…Elastic systems offer new degrees of freedom to the designer by relaxing the strict global event scheduling requirements of conventional synchronous designs and enabling the dynamic scheduling of operations based on the availability of the corresponding data [1]. This flexibility has been exploited in SoC IP integration using elastic IP wrappers [2], in hardware units synthesized from dataflow programming models [3], in massively parallel processors [4], [5], as well as in elastic coarse-grained reconfigurable arrays to schedule operations dynamically via elastic control [6].…”

Section: Introductionmentioning

confidence: 99%

Hardware primitives for the synthesis of multithreaded elastic systems

Dimitrakopoulos¹,

Seitanidis²,

Psarras³

et al. 2014

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2014

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Abstract-Elastic systems operate in a dataflow-like mode using a distributed scalable control and tolerating variablelatency computations. At the same time, multithreading increases the utilization of processing units and hides the latency of each operation by time-multiplexing operations of different threads in the datapath. This paper proposes a model to unify multithreading and elasticity. A new multithreaded elastic control protocol is introduced supported by low-cost elastic buffers that minimize the storage requirements without sacrificing performance. To enable the synthesis of multithreaded elastic architectures, new hardware primitives are proposed and utilized in two circuit examples to prove the applicability of the proposed approach.

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Elastic Circuits

Cited by 81 publications

References 109 publications

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

De-Elastisation: From Asynchronous Dataflows to Synchronous Circuits

Hardware primitives for the synthesis of multithreaded elastic systems

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