Checking delay-insensitivity: 10/sup 4/ gates and beyond

Abstract

Wire and gate delays are accounted to have equal, or nearly equal, effect on circuit behavior in modern design techniques. This paper introduces a new approach to verify circuits whose behavior is independent of component delays (delay-insensitive). It shows that for a particular way of implementing a delay-insensitive circuit, through a Null Convention Logic methodology, the complexity of the verification task might be significantly reduced. This method is implemented using Satisfiability (SAT)-solvers and is successfully tested on realistic design examples having tens of thousands of gates.

Design of a logic element for implementing an asynchronous FPGA

“…In circuits with multiple outputs, it is acceptable, according to Seitz's weak conditions [12], for some of the outputs to transition without having a complete input set present, as long as all outputs cannot transition before all inputs arrive. Observability requires that no orphans may propagate through a gate [7]. An orphan is defined as a wire that transitions during the current DATA wavefront, but is not used in the determination of the output.…”

“…This observability condition, also referred to as indicatability or stability, ensures that every gate transition is observable at the output, which means that every gate that transitions is necessary to transition at least one of the outputs. The observability condition can be relaxed through orphan analysis and still achieve self-timed behavior; however, this requires some delay analysis [7]. Furthermore, when circuits use the bit-wise completion strategy with selective input-incomplete components, they must also adhere to the completion-completeness criterion [15], which requires that completion signals only be generated such that no two adjacent DATA wavefronts can interact within any combinational component.…”

“…NCL gates can be implemented with Boolean logic by using an SR latch to achieve the hysteresis behavior [4]; however, this implementation yields potential race conditions, which may cause the SR latch to temporarily enter the metastable state or produce the incorrect output all together [3]. This becomes even more of a problem when an NCL circuit is implemented on a standard FPGA, since a single NCL gate may be comprised of multiple Boolean gates, such that the single NCL gate could be distributed over many configurable logic blocks (CLBs), yielding nonisochronic forks [5,6], or problematic orphans [7], and thus further compromising delay-insensitivity. To illustrate this point, a few NCL circuits were synthesized to a Xilinx Spartan 2 FPGA using Mentor Graphics Leonardo Spectrum tool.…”

Design of delay-insensitive three dimension pipeline array multiplier for image processing

“…In a delay-insensitive combinational circuit, any transition at the wire or gate must be acknowledged by the primary outputs O. If some gates or wires of the circuit are unable to translate the results of their firings into the changes at primary outputs, the circuit is said to contain so-called orphans [17]. Orphans localize the places of delay-insensitivity violations.…”

“…NCL is not purely DI but an extension of DI close to quasi-DI (QDI) [7,8]. NCL is based on a more general delay assumption than the isochronic fork [15] so-called "orphan" hypotheses [16,17]. Of course further improvement may be accomplished using novel dynamic logic ideas (e.g.…”