NULL Convention Logic/sup TM/: a complete and consistent logic for asynchronous digital circuit synthesis

Soft error in FPGA-implemented asynchronous circuits

“…(1,1) Invalid NCL circuits utilize dual-rail or quad-rail or quad-rail encoding technique to achieve delay insensitivity [6]. A dual-rail signal D is encoded by two wires, D 0 and D 1 , as shown in Table 1 The two rails are mutually exclusive, such that both rails can never be asserted simultaneously; this state is defined as an illegal state.…”

“…The proposed asynchronous logic, called Null Convention Logic (NCL) [6], employs dual-rail encoding for each bit to achieve the quasi-delay insensitivity of the whole circuit. The preliminary results show the unique behavior of NCL mapped into FPGAs, and thus provide a clue for possible solutions to soft error problem in FPGAs through asynchronous design at circuit level.…”

Dual-Sum Single-Carry Self-Timed Adder Designs

“…This is mainly due to the fast carry propagation resulting from weak-indication of carry outputs. Since this work relies on utilizing synchronous cells for realizing robust ST designs, comparison with [12], or improvisations based on it is not possible, as they are founded on custom macros (proprietary NCL macros) made available as part of a cell library. The method of [13] can give rise to gate orphans and so it has not been considered.…”

Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

“…These implementations are then converted in a template-based fashion (i.e. gate-by-gate) into a NullConvention Logic (NCL) [9] implementation. The final circuit is then augmented with a completion detection (CD) circuit which detects when all the gates in the circuit have reached a stable value, thus eliminating all orphans.…”