We propose a novel approach for First Impressions Recognition in terms of the Big Five personality-traits from short videos. The Big Five personality traits is a model to describe human personality using five broad categories: Extraversion, Agreeableness, Conscientiousness, Neuroticism and Openness. We train two bi-modal end-to-end deep neural network architectures using temporally ordered audio and novel stochastic visual features from few frames, without over-fitting. We empirically show that the trained models perform exceptionally well, even after training from a small sub-portions of inputs. Our method is evaluated in ChaLearn LAP 2016 Apparent Personality Analysis (APA) competition using ChaLearn LAP APA2016 dataset and achieved excellent performance.
This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (GLA) adders based on the notion of seetion-carry is discussed. Three types of GLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed GLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter ocenpies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications -here; this concept is applied to efiect latency reduction in self-timed GLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a GLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.
This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate adder with no compromise on the speed performance. For 64-bit addition, our approximate adder achieves a 24% improvement in the maximum operating frequency, and a 25% reduction in the number of LUTs utilized compared to the accurate adder (post place and route on a Virtex-7 FPGA device). We also make comparisons with the FPGA-based implementations of some well-known gate-level approximate adders, and further provide insights into the error characteristics showing that the proposed approximate adder has a reduced error range.
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