Asynchronous design using commercial HDL synthesis tools

Ligthart, M.; Fant, Karl M.; Smith, Ronan J.; Taubin, Alexander; Kondratyev, A.

doi:10.1109/async.2000.836983

Cited by 117 publications

(62 citation statements)

References 21 publications

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“…In addition to separation of optimization and timing SADT model contributes separation of set and reset phases: for example each gate in Null Convention Logic (NCL) [19] is sequential but can be presented as combinational -separately in set and reset phases. As a result in SADT flow logic optimization remains separate from sequential behavior -the reason why SADT flows can be based on standard synchronous RTL compilers.…”

Section: Asynchronous Micropipelines Synthesismentioning

confidence: 99%

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Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Kulikowski

Smirnov

Taubin

2006

Lecture Notes in Computer Science

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Abstract. Balanced dynamic dual-rail gates and asynchronous circuits have been shown, if implemented correctly, to have natural and efficient resistance to side-channel attacks. Despite their benefits for security applications they have not been adapted to current mainstream designs due to the lack of electronic design automation support and their nonstandard or proprietary design methodologies. We present a novel asynchronous fine-grain pipeline synthesis methodology that addresses these limitations. It allows synthesis of asynchronous quasi delay insensitive circuits from standard high-level hardware description language (HDL) specifications. We briefly present a proof of concept differential dynamic power balanced micropipeline library cells that are approximately 6 times more balanced than the best (differential dynamic) cells designed using previous balancing methods. An implementation of the Advanced Encryption Standard based on these balanced cells and synthesized using our tool flow shows a 6.6 times throughput improvement over the synchronous automatically pipelined implementation using the same TSMC 0.18μm technology synthesized from the same HDL specification.

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Section: Asynchronous Micropipelines Synthesismentioning

confidence: 99%

“…Inter-register handshake insertion approach where clock connected to registers is substituted by handshaking between the registers placed at the same points in the circuit (Fig. 1b) is used by NCL [19] and De-synchronization [20] flows.…”

Section: Asynchronous Micropipelines Synthesismentioning

confidence: 99%

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Kulikowski

Smirnov

Taubin

2006

Lecture Notes in Computer Science

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“…skewed) fork delays. The NCL commercial tool flow is aimed at eliminating problems due to wire orphans at the physical design level [11].…”

Section: C-4mentioning

confidence: 99%

“…The DIMS style is a simple approach to designing robust dual-rail asynchronous circuits from Boolean netlists in a template-based manner. NCL [6], [11] is a more recent approach to designing these circuits, and has been incorporated into a commercial CAD tool flow at Theseus Logic Inc. and applied to several industrial circuits. The NCL design style has been used to develop an asynchronous version of the Motorola MCORE processor [13].…”

Section: Introductionmentioning

confidence: 99%

“…The NCL design style has been used to develop an asynchronous version of the Motorola MCORE processor [13]. Also, more than 18 other chips were designed and fabricated using the NCL flow with the largest having 660,000 transistors [11]. Currently, the NCL flow is used in a DARPA CLASS project, led by Boeing, which is a major new initiative to develop commercially viable asynchronous CAD flow.…”

Section: Introductionmentioning

confidence: 99%

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Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Jeong

Nowick

2007

2007 Asia and South Pacific Design Automation Conference

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Abstract-As process, temperature and voltage variations become significant in deep submicron design, timing closure becomes a critical challenge using synchronous CAD flows. One attractive alternative is to use robust asynchronous circuits which gracefully accommodate timing discrepancies. However, these asynchronous circuits typically suffer from high area and latency overhead. In this paper, an optimization algorithm is presented which reduces the area and delay of these circuits by relaxing their overly-restrictive style. The algorithm was implemented and experiments performed on a subset of MCNC circuits. On average, 49.2% of the gates could be implemented in a relaxed manner, 34.9% area improvement was achieved, and 16.1% delay improvement was achieved using a simple heuristic for targeting the critical path in the circuit. This is the first proposed approach that systematically optimizes asynchronous circuits based on the notion of local relaxation while still preserving the circuit's overall timing-robustness.

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Asynchronous sum‐of‐products logic minimization and orthogonalization

Lemberski

Fišer

Suleymanov

2012

Circuit Theory & Apps

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We propose a method of the asynchronous sum-of-products (SOP) logic simplification that comprises of minimization and orthogonalization. The method is based on a transformation of the conventional single-rail SOP synchronous logic into the dual-rail asynchronous one operating under so-called modified weak constraints. We formulate and prove the product terms constraint that ensures a correct logic behavior. We have processed the MCNC benchmarks and generated the asynchronous SOP logic. The complexity of the logic obtained is compared with the state-of-the-art representation. Using our approach, we achieve a significant improvement.

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Asynchronous design using commercial HDL synthesis tools

Cited by 117 publications

References 21 publications

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks

Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation

Asynchronous sum‐of‐products logic minimization and orthogonalization

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